Technical Program Committee

Technical Program Chair

Atsushi Takahashi, Tokyo Institute of Technology, Japan

Technical Program Vice Chairs

Taewhan Kim, Seoul National University, Korea

Tohru Ishihara, Kyoto University, Japan

Secretaries

Shimpei Sato, Tokyo Institute of Technology, Japan

Yukihide Kohira, Aizu University, Japan

Chikaaki Kodama, Toshiba Memory, Japan

Subcommittees

* : subcommittee chairs
[1] System-Level Modeling and Design Methodology
*Preeti Ranjan Panda, Indian Institute of Technology Delhi, India
Jing-Jia Liou, National Tsing Hua University, Taiwan
Masashi Tawada, Waseda University, Japan
Akash Kumar, Technische Universitaet Dresden, Germany
Jongeun Lee, UNIST, Korea
Naehyuck Chang, KAIST, Korea
Hiroshi Nakamura, University of Tokyo, Japan
Sri Parameswaran, University of New South Wales, Australia
Keni Qiu, Capital Normal University, China
[2] Embedded System Architecture and Design
*Wei Zhang, Hong Kong University of Science and Technology, Hong Kong
Chun-Yi Lee, National Tsing Hua University, Taiwan
Yongpan Liu, Tsinghua University, China
Yun Liang, Peking University, China
Yajun Ha, ShanghaiTech University, China
Hyung Gyu Lee, Daegu University, Korea
Ji-Hoon Kim, Seoul National University of Science and Technology, Korea
Wujie Wen, Florida International University, USA
Heng Yu, United Arab Emirates University, United Arab Emirates
Hsiang-Yun Cheng, Academia Sinica, Taiwan
[3] On-chip Communication and Networks-on-Chip
*Mehdi Tahoori, Karlsruhe Institute of Technology, Germany
Jiang Xu, Hong Kong University of Science and Technology, Hong Kong
Partha Pande, Washington State University, USA
Madhu Mutyam, Indian Institute of Technology Madras, India
John Kim, KAIST, Korea
[4] Embedded Software
*Zili Shao, Hong Kong Polytechnic University, Hong Kong
Chung-Ta King, National Tsing Hua University, Taiwan
Sungjoo Yoo, Seoul National University, Korea
Jalil Boukhobza, University of Western Brittany, France
Yi Wang, Shenzhen University, China
Mengying Zhao, Shandong University, China
Franco Fummi, University of Verona, Italy
Yuan-Hao Chang, Academia Sinica, Taiwan
[5] Device/Circuit-Level Modeling, Simulation and Verification
*Jaijeet Roychowdhury, UC Berkeley, USA
Alper Demir, Koc University, Turkey
Jason C. Verley, Sandia National Laboratory, USA
Rajit Manohar, Yale University, USA
Soumyajit Mandal, Case Western Reserve University, USA
Markus Olbrich, Leibniz Universität Hannover, Germany
Mark Po-Hung Lin. National Chung Cheng University, Taiwan
[6] Power Analysis, Low Power Design, and Thermal Management
*Chia-Lin Yang. National Taiwan University, Taiwan
Cheng Zhuo, Zhejiang University, China
Jae-Joon Kim, Pohang University of Science and Technology, Korea
Masaaki Kondo, University of Tokyo, Japan
Koji Inoue, Kyushu University, Japan
Sheldon Tan, University of California at Riverside, USA
Soo Youn Kim, Dongguk University, Korea
Tsung-Te Liu, National Taiwan University, Taiwan
Joonho Kong, Kyungpook National University, Korea
[7] Logic/High-Level Synthesis and Optimization
*Zhiru Zhang, Cornell University, USA
Shouyi Yin, Tsinghua University, China
Fabrizio Ferrandi, Politecnico di Milano, Italy
Seiya Shibata, NEC, Japan
Benjamin Carrion Schafer, The University of Texas at Dallas, USA
Jie-Hong Roland Jiang, National Taiwan University, Taiwan
[8] Physical Design
*Yasuhiro Takashima, University of Kitakyushu, Japan
Seokhyeong Kang, Ulsan National Institute of Science and Technology, Korea
Hyung-Ock Kim, Samsung Electronics, Korea
Hung-Ming Chen, National Chiao Tung University, Taiwan
Masato Inagi, Hiroshima City University, Japan
Sheqin Dong, Tsinghua University, China
[9] Design for Manufacturability and Reliability
*Xuan Zeng, Fudan University, China
*Masanori Hashimoto, Osaka University, Japan
Martin Wong , University of Illinois at Urbana-Champaign, USA
Charles Chiang, Synopsys, Inc., USA
Yukihide Kohira, Aizu University, Japan
Ting-Chi Wang, National Tsing Hua University, Taiwan
Tetsuaki Matsunawa, Toshiba Memory, Japan
Takashi Sato, Kyoto University, Japan
Bong Hyun Lee, Samsung, Korea
[10] Test and Design for Testability
*Jin-Fu Li, National Central University, Taiwan
Satoshi Ohtake, Oita University, Japan
Kohei Miyase, Kyushu Institute of Technology, Japan
Seetal Potluri , Xilinx Asia Pacific Pte. Ltd., Singapore
Ying Zhang, Tongji University, China
[11] Security and Fault-Tolerant System
*Yier Jin, University of Florida, USA
Jakub Szefer, Yale University, USA
Fareena Saqib, The University of North Carolina at Charlotte, USA
Estelle Wang, Continental Automotive, Singapore
Qiaoyan Yu, University of New Hampshire, USA
Gang Qu, Unviersity of Maryland, USA
Xiaoxiao Wang, Beihang University, China
Li Shang, University of Colorado Boulder, USA
Bei Yu, Chinese University at Hong Kong, Hong Kong
[12] Emerging Technology
*Yiran Chen, Duke University, USA
Danghui Wang, Northwestern Polytechnical University, China
Shigeru Yamashita, Ritsumeikan University, Japan
Deliang Fan, University of Central Florida, USA
Po-Chun Huang, Yuan Ze University, Taiwan
Jianlei Yang, Beihang University, China
Li Jiang, Shanghai Jiao Tong University, China
Pingqiang Zhou, ShanghaiTech University, China
[13] Emerging Application
*Tsung-Yi Ho, National Tsing Hua University, Taiwan
Masanori Muroyama, Tohoku University, Japan
Noboru Yoneoka, Fujitsu Laboratories Ltd., Japan
Hailong Yao, Tsinghua University, China
Yanzhi Wang , Syracuse University, USA
Sehwan Kim, Dankook University, Korea
Younghyun Kim, University of Wisconsin–Madison, USA
Sudip Roy, Indian Institute of Technology Roorkee, India

Last Updated: Sep 26, 2017