University LSI Design Contest
The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processer, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.
This year, the University LSI Design Contest Committee received 34 high-quality designs from five countries/areas, and selected 27 designs out of them. The selected designs will be disclosed in Session 4A at three-minute presentations, followed by interactive discussions in front of their posters with light meals. For five outstanding designs, two Best Design Awards and three Special Feature Awards will be presented in the banquet. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.
- Date: Wednesday, January 24, 2018
- Oral Presentation: 10:30AM - 12:10PM (Place: Room 302)
- Poster Presentation: 12:10PM - 13:40PM (Place: Lobby 3F)
- Co-chairs: Minkyu Je (KAIST), Ikjoon Chang (Kyunghee University), Makoto Ikeda (University of Tokyo)
- University LSI design contest committee
- UDC session schedule (html-version)
| Title |
|
| 4A-1 | An Ultra-Low-Noise Differential Relaxation Oscillator based on a Swing-Boosting Scheme |
| 4A-2 | A Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag with Per-Query Key Update and Power-Glitch Attack Countermeasures |
| 4A-3 | A 42nJ/conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-ion Batteries |
| 4A-4 | A Supply Noise Insensitive PLL with a Rail-to-Rail Swing Ring Oscillator and a Wideband Noise Suppression Loop |
| 4A-5 | A Dual-Output SC Converter with Dynamic Power Allocation for Multi-Core Application Processors |
| 4A-6 | 12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-Panel Interface |
| 4A-7 | A Digital SC Converter with High Efficiency and Low Voltage Ripple |
| 4A-8 | A Reconfigurable SIMO System with 10-Output Dual-Bus DC-DC Converter using the Load Balancing Function in Group Allocator for Diversified Load Condition |
| 4A-9 | Real-time Depth Map Processor for Offset Aperture based Single Camera System |
| 4A-10 | Edge Pursuit Comparator with Application in a 74.1dB SNDR, 20KS/s 15b SAR ADC |
| 4A-11 | A 300-μW Audio ΔΣ Modulator With 100.5-dB DR Using Dynamic Bias Inverter |
| 4A-12 | An External-Capacitor-Less High PSR Low-Dropout Regulator Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate |
| 4A-13 | A 230-260GHz Wideband Amplifier in 65nm CMOS Based on Dual-Peak Gmax-core |
| 4A-14 | An Injection-Locked Frequency Multiplier with a Continuous Frequency-Tracking Loop for 5G Transceivers |
| 4A-15 | A 6.9mW 120fps 28×50 Capacitive Touch Sensor for 1mm-φ Stylus Using Current-Driven ΔΣ ADCs |
| 4A-16 | A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique |
| 4A-17 | A 9.3 nW All-in-One Bandgap Voltage and Current Reference Circuit using Leakage-based PTAT Generation and DIBL Characteristic |
| 4A-18 | "A 16.6-pJ/b 150-Mb/s Body-Channel Communication Transceiver with Decision Feedback Equalization Improving >200x Area Efficiency |
| 4A-19 | Low Power FSK Transceiver using ADPLL with direct modulation and integrated SPDT for BLE Application |
| 4A-20 | A 2.22 Gbps Non-Binary LDPC Decoder with Aggressive Overlap Scheduling in 65nm CMOS |
| 4A-21 | Design of Resource Sharing Reconfigurable delta sigma SAR-ADC |
| 4A-22 | A 2.4GHz, -102dBm-Sensitivity, 25kb/s, 0.466mW Interference Resistant BFSK Multi-Channel Sliding-IF ULP Receiver |
| 4A-23 | Highly Sensitive Fingerprint Readout IC for Glass-Covered Mutual Capacitive Fingerprint Sensor |
| 4A-24 | A 5.8 GHz DSRC Digitally Controlled CMOS RF-SoC Transceiver for China ETC |
| 4A-25 | A Low-Power Wide Dynamic-Range Current Readout Circuit for Biosensors |
| 4A-26 | An Efficient Fixed-point Arithmetic Processor Using A Hybrid CORDIC Algorithm |
| 4A-27 | A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH Decoder in 65nm CMOS for NAND Flash Storage Systems |