Special Session (SS) and Industry Session (IS)

Date/Time Title
SS-1 Tuesday, January 23,
11:00-12:15		 Deep Learning for Applications that Live on Big Data
SS-2 Tuesday, January 23,
13:45-15:25		 New Advances in Hardware Security
IS Wednesday, January 24,
13:40-15:45		 Machine/Deep Learning for Semiconductor Design, EDA Technologies, and Application
SS-3 Wednesday, January 24,
16:15-17:30		 Training Deep Neural Networks: Algorithms and Architectures Machine/Deep
SS-4 Thursday, January 25,
10:30-11:45		 Reliability and Aging-Aware Designs for sub-10nm ICs
SS-5 Thursday, January 25,
10:30-11:45		 Design Automation and Methodology for Flexible Electronics

SS-1: Deep Learning for Applications that Live on Big Data

  • Organizer: Deming Chen, ECE, UIUC
  • Time: Tuesday, January 23, 11:00-12:15
  • Location: Room 302
  1. Quantized Deep Neural Networks for Energy Efficient Hardware-based Inference
    Ruizhou Ding, Zeye Liu, Shawn Blanton, Diana Marculescu (Carnegie Mellon Univ., USA)
  2. Intelligent Corner Synthesis via Cycle-Consistent Generative Adversarial Networks for Efficient Validation of Autonomous Driving Systems
    Handi Yu (Duke Univ., USA), Xin Li (Duke Univ. / Duke Kunshan Univ., USA)
  3. Deep Learning for Better Variant Calling for Cancer Diagnosis and Treatment
    Anand Ramachandran, Huiren Li, Eric Klee, Steven Lumetta, Deming Chen (UIUC, USA)

SS-2: New Advances in Hardware Security

  • Organizer: Gang Qu, Univ. of Maryland
  • Time: Tuesday, January 23, 13:45-15:25
  • Location: Room 302
  1. Effect of Aging on Linear and Nonlinear MUX PUFs by Statistical Modeling
    Anoop Koyily, S.V. Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi (Univ. of Minnesota, USA)
  2. ASAX: Automatic Security Assertion Extraction for Detecting Hardware Trojans
    Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang (Tsinghua Univ., China)
  3. Polymorphic Gate based IC Watermarking Techniques
    Tian Wang, Xiaoxin Cui, Dunshan Yu (Peking Univ., China), Omid Aramoon, Gang Qu (Univ. of Maryland, USA)
  4. A Machine Learning Attack Resistant Multi-PUF Design on FPGA
    Qingqing Ma (Nanjing Univ. of Aeronautics and Astronautics, China), Chongyan Gu, Neil Hanley (Queen's Univ. Belfast, U.K.), Chenghua Wang, Weiqiang Liu (Nanjing Univ. of Aeronautics and Astronautics, China), Maire O'Neill (Queen's Univ. Belfast, U.K.)

IS: Machine/Deep Learning for Semiconductor Design, EDA Technologies, and Application

  • Organizer: Kyu Myung Choi, ECE, Seoul National University
  • Time: Wednesday, January 24, 13:40-15:45
  • Location: Room 302
  1. New Directions for Learning-Based IC Design Tools and Methodologies
    Andrew B. Kahng, Lutong Wang (UCSD, USA)
  2. Machine Learning and Systems for Building the Next Generation of EDA tools
    Manish Pandey (Synopsys, USA)
  3. Machine Learning based Generic Violation Waiver System with Application on Electromigration Sign-off
    Norman Chang, Ajay Baranwal, Hao Zhuang, Ming-Chih Shih, Rahul Rajan, Yaowei Jia, Hui-Lun Liao, Ying-Shiun Li (Ansys, USA), Ting Ku, Rex Lin (Nvidia, USA)
  4. Machine Learning for Engineering
    Jeff Dyck (Solido Design Automation, USA)
  5. Large-scale Long-term Urban Taxi Traffic Demand Forecasting Using Deep Learning
    Siyu Liao (City Univ. of New York, USA), Liutong Zhou, Xuan Di (Columbia Univ., USA), Bo Yuan (City Univ. of New York, USA), Jinjun Xiong (IBM, USA)

SS-3: Training Deep Neural Networks: Algorithms and Architectures

  • Organizer: Kiyoung Choi, ECE, Seoul National University
  • Time: Wednesday, January 24, 16:15-17:30
  • Location: Room 302
  1. Accelerator-Centric Deep Learning Systems for Enhanced Scalability, Energy-Efficiency, and Programmability
    Minsoo Rhu (POSTECH, Korea)
  2. Running Sparse and Low-Precision Neural Network: When Algorithm Meets Hardware
    Yiran Chen (Duke Univ., USA)
  3. Architectures and Algorithms for User Customization of CNNs
    Bernhard Egger (Seoul National Univ., Korea)

SS-4: Reliability and Aging-Aware Designs for sub-10nm ICs

  • Organizer: Sheldon Tan, UC Riverside
  • Time: Thursday, January 25, 10:30-11:45
  • Location: Room 401
  1. Accelerating Electromigration Aging for Fast Failure Detection for Nanometer ICs
    Zeyu Sun, Sheriff Sadiqbatcha, Sheldon Tan (Univ. of California, Riverside, USA)
  2. Efficient Worst-Case Timing Analysis of Critical-Path Delay under Workload-Dependent Aging Degradation
    Shumpei Morita, Song Bian (Kyoto Univ., Japan), Michihiro Shintani (NARA Inst. of Science and Tech., Japan), Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
  3. Balancing Resiliency and Energy Efficiency of Functional Units in Ultra-Low Power Systems
    Mohammad Saber Golanbari, Anteneh Gebregiorgis, Elyas Moradi, Saman Kiamehr, Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)

SS-5: Design Automation and Methodology for Flexible Electronics

  • Organizer: Mehdi Tahoori, Karlsruhe Institute of Technology, Jim Huang, Hewlett Packard Labs
  • Time: Thursday, January 25, 10:30-11:45
  • Location: Room 402A
  1. Mechanical Strain and Temperature Aware Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array
    Wenyu Sun, Yuxuan Huang, Qinghang Zhao, Fei Qiao (Tsinghua Univ., China), Xiaojun Guo (Shanghai Jiao Tong Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Huazhong Yang, Yongpan Liu (Tsinghua Univ., China)
  2. Process Design Kit for Flexible Hybrid Electronics
    Leilai Shao (UCSB, USA), Tsung-Ching Huang (Hewlett Packard Labs, USA), Ting Lei, Zhenan Bao (Stanford Univ., USA), Raymond Beausoleil (UCSB, USA), Kwang-Ting Cheng (Hong-Kong Univ. of Science and Tech., China)
  3. From Silicon to Printed Electronics: A Coherent Modeling and Design Flow Approach Based on Printed Electrolyte Gated FETs
    Gabriel Cadilha Marques, Farhan Rasheed, Jasmin Hagmann-Aghassi, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Last Updated: October 25, 2017