1001 "FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter"
1008 "An Exact Schedulability Analysis for Global Fixed-Priority Scheduling of the AER Task Model"
1011 "Latent Weight-based Pruning for Small Binary Neural Networks"
1012 "Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack Memory"
1017 "Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning"
1018 "COLAB: Collaborative and Efficient Processing of Replicated Cache Requests in GPU"
1019 "AutoFlex: Unified Evaluation and Design Framework for Flexible Hybrid Electronics"
1024 "Quantum Data Compression for Efficient Generation of Control Pulses"
1028 "Safety-driven Interactive Planning for Neural Network-based Lane Changing"
1029 "PAALM: Power Density Aware Approximate Logarithmic Multiplier Design"
1031 "System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms"
1032 "Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study"
1047 "Hardware Trojan Detection Using Shapley Ensemble Boosting"
1048 "CNFET7: An Open Source Cell Library for 7-nm CNFET Technology"
1049 "Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects"
1052 "On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC"
1055 "Graph Partitioning Approach for Fast Quantum Circuit Simulation"
1057 "Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars"
1060 "Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency"
1066 "Static Probability Analysis Guided RTL Hardware Trojan Test Generation"
1074 "Multi-Wavelength Parallel Training and Quantization-Aware Tuning for WDM-Based Optical Convolutional Neural Networks ConsideringWavelength-Relative Deviations"
1076 "Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication"
1084 "MIA-aware Detailed Placement and VT Reassignment for Leakage Power Optimization"
1086 "Efficient Global Optimization for Large Scaled Ordered Escape Routing"
1091 "DPRoute: Deep Learning Framework for Package Routing"
1093 "Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models"
1094 "Mixed-Traffic Intersection Management Utilizing Connected and Autonomous Vehicles as Traffic Regulators"
1096 "A SAT Encoding for Optimal Clifford Circuit Synthesis"
1097 "Discovering the In-Memory Kernels of 3D Dot-Product Engines"
1103 "ReMeCo: Reliable memristor-based in-memory neuromorphic computation"
1104 "Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers"
1109 "TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers"
1111 "Compilation of Entangling Gates for High-Dimensional Quantum Systems"
1112 "Exploiting Reversible Computing for Verification: Potential, Possible Paths, and Consequences"
1115 "Hardware Trojan Detection and High-Precision Localization in NoC-based MPSoC using Machine Learning"
1118 "Mixed-Criticality with Integer Multiple WCETs and Dropping Relations: New Scheduling Challenges"
1120 "BufFormer: A Generative ML Framework for Scalable Buffering"
1122 "Automatic Test Pattern Generation and Compaction for Deep Neural Networks"
1126 "A Flexible ASIC-oriented Design for a Full NTRU Accelerator"
1139 "Optimizing Data Layout for Racetrack Memory in Embedded Systems"
1140 "Rethink before Releasing your Model: ML Model Extraction Attack in EDA"
1141 "Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction"
1153 "Mortar: Mophing the Bit Level Sparsity for General Purpose Deep Learning Acceleration"
1156 "An Equivalence Checking Framework for Agile Hardware Design"
1158 "Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient In-Memory Acceleration"
1159 "Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware Architectures"
1160 "An SMT-Solver-based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates"
1161 "Semantic Guided Fine-grained Point Cloud Quantization Framework for 3D Object Detection"
1165 "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration"
1170 "DependableHD: A Hyperdimensional Learning Framework for Edge- oriented Voltage-scaled Circuits"
1172 "EO-Shield: A Multi-function Protection Scheme against Side Channel and Focused Ion Beam Attacks"
1176 "A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks"
1177 "Equivalence Checking of Parameterized Quantum Circuits: Verifying the Compilation of Variational Quantum Algorithms"
1179 "NTGAT: A Graph Attention Network Accelerator with Runtime Node Tailoring"
1188 "WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code"
1190 "ASSURER: A PPA-friendly Security Closure Framework for Physical Design"
1191 "Software Tools for Decoding Quantum Low-Density Parity Check Codes"
1193 "An On-line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs"
1197 "Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-sharing Approach"
1199 "An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems"
1205 "Quantization Through Search: A Novel Scheme to Quantize Convolutional Neural Networks in Finite Weight Space"
1208 "Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits"
1209 "Efficient System-Level Design Space Exploration for High-Level Synthesis using Pareto-Optimal Subspace Pruning"
1213 "A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential"
1214 "Approximating HW Accelerators through Partial Extractions onto shared Artificial Neural Networks"
1217 "Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics"
1221 "An Efficient Near-Bank Processing Architecture for Personalized Recommendation System"
1222 "PMU-Leaker: Performance Monitor Unit-based Realization of Cache Side- Channel Attacks"
1226 "RVComp: Analog Variation Compensation for RRAM-based In-Memory Computing"
1236 "SLOGAN: SDC probability estimation using structured graph attention network"
1237 "A Robust Approach to Detecting Non-equivalent Quantum Circuits Using Specially Designed Stimuli"
1238 "Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee"
1242 "High Dimensional Yield Estimation using Shrinkage Deep Features and Maximization of Integral Entropy Reduction"
1247 "A Robust FPGA Router with Concurrent Intra-CLB Rerouting"
1248 "Agile Hardware and Software Co-design for RISC-V-based Multi-precision Deep Learning Microprocessor"
1249 "MUGNoC: A Software-configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows"
1251 "An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction"
1261 "Toward Energy-Efficient Sparse Matrix-Vector Multiplication with Near STT-MRAM Computing Architecture"
1262 "Parallel Incomplete LU Factorization Based Iterative Solver for Fixed- Structure Linear Equations in Circuit Simulation"
1269 "Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis"
1281 "Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization"
1287 "Accelerated Capacitance Simulation of 3-D Structures With Considerable Amounts of General Floating Metals"
1295 "DECC: Differential ECC for Read Performance Optimization on High- Density NAND Flash Memory"
1303 "Optimization of Reversible Logic Networks with Gate Sharing"
1315 "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors using DNN Learning"
1316 "Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-based DNN Accelerators"
1320 "RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability"
1325 "A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits"
1329 "Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU"
1334 "SHarPen: SoC Security Verification by Hardware Penetration Test"
1337 "CompaSeC: A Compiler-assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V"
1340 SecHLS: Enabling Security Awareness in High-Level Synthesis"
1342 "Data-Model-Circuit Tri-design for Ultra-light Video Intelligence on Edge Devices"
1356 "Knowledge Distillation in Quantum Neural Network using Approximate Synthesis"
1365 "MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy"
1372 "Area-driven FPGA Logic Synthesis Using Reinforcement Learning"
1373 "RIMAC: An Array-level ADC/DAC-free ReRAM-based In-Memory DNN Processor with Analog Cache and Computation"
1374 "EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation"
1388 "Exploring Architectural Implications to Boost Performance for in-NVM B+- tree"
1390 "Safety-Aware Flexible Schedule Synthesis for Cyber-Physical Systems using Weakly-Hard Constraints"
1392 "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks"
1398 "Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs"