Keynote Addresses

The venue for the keynote addresses is Miraikan Hall.

Opening & Keynote I : Tuesday, January 21, 9:00-9:45

Design Innovation and Collaboration with Foundries: Towards a Sustainable Semiconductor Industry

Kazunari Ishimaru

Senior Managing Executive Officer, Head of Silicon Technology Division
Rapidus Corporation, Japan

Abstract:
As the semiconductor industry faces mounting pressure to meet both rising demand and sustainability challenges, the need for innovative design and effective collaboration with foundries has never been more critical.
The lead time from design to productization is becoming longer with each transition to the next generation, which is particularly critical in the rapidly growing AI market, where time to market is crucial. Additionally, traditional DFM (Design for Manufacturability) to address the increasingly complex device structures and manufacturing processes is also becoming more complicated, leading to longer design periods.
As a foundry, it is essential to provide feedback to the design space from a manufacturing perspective, and the realization of MFD (Manufacturing for Design) will become essential in the future. The DMCO (Design-Manufacturing Co-Optimization) proposed by Rapidus is a method to solve this issue, and collaboration with customers and ecosystem partners is crucial. Furthermore, collaborative efforts with foundries enable adopting sustainable production practices, such as reducing energy consumption, minimizing waste, and ensuring supply chain transparency.
The importance of integrating design innovation and foundry collaboration to build a semiconductor industry that is resilient, responsible, and aligned with global sustainability objectives.

Biography:
Dr. Kazunari Ishimaru joined Toshiba, Semiconductor Device Engineering Labs. in 1988 and engaged in the development of advanced SRAM/Logic technologies. He was a visiting industrial fellow at the University of California at Berkeley from 1997 to 1998. He was transferred to Toshiba America Electric Components Inc. in 2006 as a Vice President of Research, where he led the development of 32nm~20nm CMOS platform technologies with IBM as project leader from Toshiba. After returning to Japan in 2010, he was in charge of logic product manufacturing at Oita operation as a senior manager. In 2013, he moved to the Center for Semiconductor Research and Development of Toshiba Semiconductor Company as a senior manager of the Advanced Memory Technology Development Dept. He became a Director of the Institute of Memory Technology R&D at Kioxia Corporation in 2022, and joined Rapidus Corporation in April 2023. He served as IEDM General Chair in 2011. He also served as a Scientific Advisory Board member of IMEC from 2014 to 2018. He was elevated to IEEE Fellow in 2014.

Keynote II : Wednesday, January 22, 9:00-9:45

Compilation and Architecture Optimization for Quantum Computing

Jason Cong

UCLA Computer Science Department
Director, Center for Domain-Specific Computing (CDSC)

Abstract:
The rapid progress in quantum computing (QC) technologies in the past decade led to QC processors with hundreds to thousands of qubits. As a result, efficient compilation flow become both important and challenging. In this talk, I focus on the critical step of the compilation called quantum layout synthesis (QLS), which determines the space and time of computation of a quantum circuit. I first show that the existing QLS solutions, surprisingly, are far away from optimal, despite the effort of the research community for more than a decade. Then, I present recent progress on scalable and highly optimized QLS solutions for both QC processors with fixed connectivity, such as those based on the superconducting technology, and those with programmable connectivity, such as those using neutral atom arrays. Finally, I shall discuss how such optimized QLS tools can be used to guide QC processor architecture optimization, e.g. in determining the number of movable lasers and the configuration of storage vs computing zones for neutral atom arrays.

Biography:
JASON CONG is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department (and a former department chair), with joint appointment from the Electrical and Computer Engineering Department. He is the director of Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing. He has over 500 publications in these areas, including 18 best paper awards, and 4 papers in the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS and Vitis HLS after Xilinx’s acquisition). He is member of the National Academy of Engineering, the American Academy of Arts and Sciences, and a Fellow of ACM, IEEE, and the National Academy of Inventors. He is recipient of the SIA University Research Award, the EDAA Achievement Award, the IEEE Robert N. Noyce Medal for “fundamental contributions to electronic design automation and FPGA design methods”, and most recently the Phil Kaufman Award for “sustained fundamental contributions FPGA design automation technology, from circuit to system levels, with widespread industrial impact.

Keynote III : Thursday, January 23, 9:00-9:45

In-Memory Computing-based Deep Learning Accelerators: An Overview and Future Prospects

Abu Sebastian

IBM Research Europe – Zurich

Abstract:
Analog in-memory computing (AIMC), where synaptic weights are stored in nanoscale non-volatile memory elements and computations are carried out in the analogue or mixed-signal domain, represents a promising approach for developing the next generation of deep learning accelerators. In the first part of the presentation, I will explore the current advancements in this area, focusing on a 64-core AIMC chip built using 14nm CMOS technology with integrated phase-change memory. This chip achieves classification accuracy comparable to floating-point operations and demonstrates seamless integration of analogue and digital processing units. This work lays the foundation for a heterogeneous mixed-signal architecture. In the second part, I will cover ongoing efforts to design the next generation of AIMC chips for deep learning inference, targeting both edge and cloud applications.

Biography:
Dr. Abu Sebastian is a Distinguished Scientist and technical manager at IBM Research – Zurich. He is one of the technical leaders of IBM’s research efforts towards next generation AI Hardware and manages the in-memory computing group at IBM Research - Zurich. He is the author of over 200 publications in peer-reviewed journals/conference proceedings and holds over 90 US patents. In 2015 he was awarded the European Research Council (ERC) consolidator grant and in 2020, he was awarded an ERC Proof-of-concept grant. He was an IBM Master Inventor and was named Principal and Distinguished Research Staff Member in 2018 and 2020, respectively. In 2019, he received the Ovshinsky Lectureship Award for his contributions to "Phase-change materials for cognitive computing". In 2023, he was conferred the title of Visiting Professor in Materials by University of Oxford. He is a distinguished lecturer and fellow of the IEEE.