ACM SIGDA Student Research Forum at ASP-DAC 2025 (SRF@ASP-DAC 2025)
Accepted Posters
| Poster ID | Title | Authors and Affiliation |
| 1 | Securing the Test Infrastructure of SoCs | Anjum Riaz, Satyadev Ahlawat (Indian Institute of Technology Jammu, India) |
| 2 | FastGDBN: A Lightning DNN-Based Good Die-in-Bad-Neighborhood Methodology through GPU Acceleration | YU-HENG TSAO, YU-GUANG CHEN (National Central University, Taiwan) |
| 3 | Evaluation of Approximate Multipliers on Convolutional Neural Networks | Ke Ma, Shinichi Nishizawa, Shinji Kimura (Waseda University, Japan) |
| 4 | Pushing the Limit of Early-Stage Multi-bit Flip-Flops Clustering | Yichen Cai (Shanghai Jiao Tong University, China), Xinfei Guo (Shanghai Jiao Tong University & State Key Laboratory of Integrated Chips and Systems (SKLICS), China) |
| 5 | Automate Analog and Mixed-Signal Circuits: From Schematic to Post-layout | Xiaohan Gao, Yibo Lin (Peking University, China) |
| 6 | Learning-based Predictions for EDA Shift-left Paradigm | Linyu Zhu, Xinfei Guo (Shanghai Jiao Tong University, China) |
Sponsors
Cadence Design Systems, Inc.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For, with additional recognitions across 13 different countries, including the World's Best Multinational Workplaces recognition and Asia's Best Workplaces!
POSTER GUIDELINES
SRF presenters are required to present a poster describing their workduring the designated SRF session to discuss their work with interested attendees. Each author is allocated a 1,194mm tall x 914mm wide (47'' tall x 36'' wide) area for a poster in A0 format. Poster sessions will run for one and half hour. Poster authors are welcome to distribute additional material to interested attendees at the poster session. Such material can include extended abstracts and whitepapers.
- One poster board is allocated to each presentation.
- Posters must be mounted using push pins provided by the organizing committee.
- Do not use foam core material for your poster or any other thick/heavy material.
- Poster presenters are responsible for printing their own poster and carrying it to the conference.
- Submit electrical data of poster to the system (see below) as a backup.
Submission Deadline: December 10, 2024
Date of Acceptance Notification: December 20, 2024
Deadline of application for visa support: December 22, 2024
Poster Submission Deadline: January 5, 2025
Poster submission website: https://tsys.jp/aspdac-srf/cgi/add_file.cgi
Forum Date: January 21 (Tue.), 2025
CONTACT INFORMATION
For queries, please send an e-mail to Prof. Heechun Park (h.park@unist.ac.kr) and Prof. Yanjing Li (yanjingl@uchicago.edu). Please include "SRF@ASP-DAC 2025" in the subject of your email.
Organizers
- Chair:
- Heechun Park, Ulsan National Institute of Science and Technology (UNIST), Korea
- Yanjing Li, University of Chicago, US
- Technical Committee:
- Muhammad Alfian Aamrizal, (UGM, Indonesia)
- Ateet Bhalla (Independent Technology Consultant, India)
- Daijoon Hyun (Sejong University, Korea)
- Yanjing Li (University of Chicago, USA)
- Heechun Park (Ulsan National Institute of Science and Technology (UNIST), Korea)
- Taigon Song (Kyungpook National University, Korea)
- ASP-DAC liaison:
- Shinichi Nishizawa, Waseda University, Japan
- Masato Inagi, Hiroshima City University, Japan