Tutorials
ASP-DAC 2025 offers attendees a set of three-hour intense introductions to specific topics. If you register for the conference, you have the option to select two out of the four topics. T2 is a session with hands-on training.
- Date: Monday, January 20, 2025 (9:30 — 17:30)
| Room Saturn | Innovation Hall | |
| 9:30 — 12:30 (JST) | Tutorial-1 Automation of Standard Cell Layout Generation and Design-Technology Co-optimization |
Tutorial-2 AHS: An EDA toolbox for Agile Chip Front-end Design |
| 14:30 — 17:30 (JST) | Tutorial-3 MBIST: Advanced Techniques for SoC Design and Verification (14:30-16:30) |
Tutorial-4 Efficient Deployment of Large Language Models on Resource-Constrained Edge Computing Platforms |
Tutorial-1: Monday, January 20, 9:30—12:30 (JST) @ Room Saturn
Automation of Standard Cell Layout Generation and Design-Technology Co-optimization
- Speakers:
- Taewhan Kim (Seoul National University)
Abstract:
As the technology advances, the design rules to be considered in standard cell layout generation become much complex and the count increases very rapidly. Moreover, at the advanced nodes, it becomes much slow or very difficult to achieve the objective i.e., to deliver or find the best-yield target node design rules while ensuring PPA-excellent target chip implementation. This is the reason why, from the EDA perspective, the need for automatic cell layout generation is inevitable at the advanced nodes, and design and technology co-optimization is a key enabling technique to achieve the chip PPA objective.In this respect, this tutorial covers EDA research area regarding two topics: (1) automation of standard cell layout generation and (2) methodologies of design and technology co-optimization utilizing diverse cell layout structures.
For standard cells, starting from the detailed layer-by-layer structure for cell layout synthesis, the complex design rules, the algorithms of cell synthesis including transistor placement and in-cell routing, and existing cell generation tools developed so far in academia with comparison of their distinct features and pros/cons will be covered. In addition, new EDA challenge of cell generation for next generation of BEOL and FEOL technologies will be discussed. For DTCO, starting from the DTCO concept utilizing standard cells, noticeable DTCO works focusing on, for target chip PPA improvement, multi-bit flip-flop cells, cells with pin inaccessibility, and cells with metal and gate poly misalignment will be covered.
Biographies:
Taewhan Kim received the B.S. degree in computer science and statistics and the M.S. degree in computer science from Seoul National University, and the Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign. He is currently a Professor with the Department of Electrical and Computer Engineering in Seoul National University. He has published over 300 technical papers in the IEEE/ACM sponsored international journals and conferences. His current research interests include computer aided design of integrated circuits ranging from the architectural synthesis through physical designs, specifically focusing on logic and physical synthesis and automatic cell layout generation. He is currently serving on Associate Editors of Integration -VLSI Journal. He served the general chair of ASP-DAC24.
Tutorial-2: Monday, January 20, 9:30—12:30 (JST) @ Innovation Hall
AHS: An EDA toolbox for Agile Chip Front-end Design
- Speaker:
- Yun (Eric) Liang (Peking University)
Youwei Xiao (Peking University)
Ruifan Xu (Peking University)
Abstract:
Compared to software design, hardware design is more expensive and time-consuming. This is partly because software community has developed a rich set of modern tools to help software programmers to get projects started and iterated easily and quickly. However, the tools are seriously antiquated and lacking for hardware design. Modern digital chips are still designed manually using hardware description language such as Verilog or VHDL, which requires low-level and tedious programming, debugging, and tuning. In this tutorial, we will introduce AHS: An EDA toolbox for Agile Chip Front-end Design, which includes various EDA tools for both chip design and verification.Biography:
Yun (Eric) Liang is currently an Endowed Boya Distinguished Professor in the School of Integrated Circuit and EECS at Peking University. His research interest is at the hardware-software interface with work spanning electronic design automation (EDA), hardware and software co-design, and reconfigurable computing. He has authored over 100 scientific publications in the leading international journals and conferences. His research has been recognized with four Best Paper Awards and six Best Paper Award Nominations. He currently serves as Associate Editor of the ACM Transactions on Embedded Computing Systems (TECS) and ACM Transactions on Reconfigurable Technology and Systems (TRETS). He was the program chair of 30th Annual IEEE International Conference on Application-specific Systems, Architecture and Processors (ASAP) 2019 and the International Conference on Field Programmable Technology (FPT) 2022. He currently serves in the program committees in the premier conferences including DAC, ICCAD, FPGA, FCCM, HPCA, MICRO, ASPDAC, etc.
Youwei Xiao is a third-year Ph.D. student at Peking University, China. His research interests include agile hardware design and compiler optimization.
Ruifan Xu is a fourth-year Ph.D. student at Peking University, China. His research interests include high-level synthesis and hardware design for AI.
Tutorial-3: Monday, January 20, 14:30—16:30 (JST) @ Room Saturn
Memory Built-In Self-Test (MBIST): Advanced Techniques for SoC Design and Verification
- Speakers:
- Prashant Seetharaman (Siemens Digital Industries Software)
Abstract:
As System-on-Chip (SoC) designs continue to grow in complexity and memory density, ensuring the reliability and testability of embedded memories becomes increasingly critical. This tutorial presents an in-depth exploration of Memory Built-In Self-Test (MBIST), a powerful methodology for testing and diagnosing memory faults in modern SoC designs. We will discuss the fundamentals of MBIST, advanced implementation techniques, and emerging trends in the field. The tutorial also covers key aspects of MBIST, including architecture, test algorithm selection, integration in the SoC design flow, and strategies for optimizing test coverage and reducing test time. Through theoretical analysis and practical examples, we will demonstrate how MBIST addresses the challenges of testing high-density memories in complex SoCs, balancing test quality, silicon area overhead, and test time to achieve optimal results in real-world scenarios. Additionally, we explore the application of MBIST to emerging memory technologies encompassing non-volatile memories and resistive RAMs. Finally, we will discuss future directions in memory testing, including the use of machine learning and artificial intelligence techniques.Biographies:
Prashant Seetharaman is a seasoned professional in the field of Design for Testability (DFT) and semiconductor technology. With over 7 years of experience, he currently serves as a Technology Enablement Engineer for the Tessent product family at Siemens Digital Industries Software, specializing in Memory Built-In Self-Test (MBIST) solutions. Prashant holds an M.S. degree in Electrical Engineering and Computer Sciences from the University of California, Berkeley and San Francisco State University.His academic background, combined with his industry experience, has shaped his expertise in memory testing, built-in test technologies for DFT logic, defect modeling, non-volatile memory analysis, silent data corruption, and the application of machine learning in VLSI. As a Technology Enablement Engineer and AI evangelist at Siemens, Prashant excels in delivering innovative and robust DFT solutions such as Shared Bus automation support in leading DFT conferences. He has also presented on a workshop for Silicon Lifecycle Management at ITC 2021. His core competencies include RTL development, and he has a strong foundation in semiconductor IC design flow, with a particular focus on memory BIST, repair, and diagnosis. Prashant's contributions have significantly impacted product adoption and customer satisfaction. In his current role, Prashant is at the forefront of using advanced DFT and silicon bring-up techniques to accelerate AI chip designs. He establishes key requirements for DFT solutions that enable the fastest time-to-market in AI chips. His expertise in machine learning allows him to stay abreast of market trends, advances in core technology, and university research in AI, which he leverages to identify partnership opportunities and new user experiences for Siemens' customers.
Prashant is an active member of several professional organizations, including the IEEE Computer Society, Society of Advanced Optics and Photonics (Optica), and IEEE Circuits and Systems Society.
Tutorial-4: Monday, January 20, 14:30—17:30 (JST) @ Innovation Hall
Efficient Deployment of Large Language Models on Resource Constrained Edge Computing Platforms
- Speaker:
- Yiyu Shi (University of Notre Dame)
Abstract:
Scaling laws guide the design of large language models (LLMs), assuming unlimited computing resources, but this is impractical for deploying personalized LLMs on resource-constrained edge devices. Critical questions arise regarding trade-offs between design factors?such as learning methods, data volume, model size, compression techniques, and training time?and their impact on efficiency and accuracy. This tutorial provides comprehensive guidelines for deploying LLMs on constrained devices and explores how advanced hardware architectures like Compute-in-Memory (CiM) can aid this process. Attendees will learn to make informed decisions on key topics like choosing between compressed vs. uncompressed LLMs, selecting appropriate personalization techniques, and optimizing training time under resource limitations.Biography:
Yiyu Shi is currently a professor in the Department of Computer Science and Engineering at the University of Notre Dame, a visiting scientist at Boston Children's Hospital and Havard Medical School, the site director of National Science Foundation I/UCRC Alternative and Sustainable Intelligent Computing, and the director of the Sustainable Computing Lab (SCL). He received his B.S. in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively. His current research interests focus on hardware intelligence and biomedical applications, with close to a dozen publications in Nature and Science research journals such as Nature Machine Intelligence, Nature Intelligence and Nature Communications. In recognition of his research, more than a dozen of his papers have been nominated for or awarded as the best paper in top journals and conferences, including the 2023 ACM/IEEE William J. McCalla ICCAD Best Paper Award and 2021 IEEE Transactions on Computer-Aided Design Donald O Pederson Best Paper Award. He is also the recipient of Facebook Research Award, IBM Invention Achievement Award, NSF CAREER Award, IEEE Region 5 Outstanding Individual Achievement Award, IEEE Computer Society Mid-Career Research Achievement Award, among others. He has served on the technical program committee of many international conferences. He is the deputy editor-in-chief of IEEE VLSI CAS Newsletter, and an associate editor of various IEEE and ACM journals. He is an IEEE CEDA distinguished lecturer and an ACM distinguished speaker.