University LSI Design Contest
The University LSI Design Contest is a unique program at ASP-DAC. The contest aims to encourage research in LSI design at universities and connect the EDA community with LSI designers by providing opportunities to present and discuss innovative and state-of-the-art designs. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processor, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.
This year, 17 excellent designs will be presented, covering AI and image accelerators, brain-machine interface, power management, ADC, wireless communication, bio-detecting, and EEG sensing. The selected designs will be discussed on January 21 with short presentations and an interactive poster session. The interactive session will be held during lunchtime so you can enjoy the poster session with the delicious food. Please come and enjoy the cutting-edge design techniques. The opening session will present the Best Design Award and two Special Feature Awards for three outstanding designs. We sincerely acknowledge the contributions of all programm committee and organizing committee members. We earnestly believe in promoting and enhancing research and education of LSI design in academic organizations through collaboration between circuit and EDA researchers. Please join the University LSI Design Contest and enjoy the stimulating discussions.
- Date: Tuesday, January 21, 2025
- Oral Presentation: Session 2F, Miraikan Hall (13:15 ~ 15:20)
- Poster Presentation: Room Jupiter (11:45 ~ 13:15)
- University LSI design contest committee
Oral Presentation Guide:
Each presenter will present their work within 5 minutes. The purpose is to share the key ideas of your design so that the interested audience can catch up with you later. Please prepare your slides carefully to communicate the important messages effectively.
Poster Presentation Guide:
Poster panels will be prepared on January 21. Please put your poster on the panel in the morning. Please take the poster off after the poster session.
UDC presenters are required to present a poster describing their work during the designated UDC session to discuss their work with interested attendees. Each author is allocated a 1,194mm tall x 914mm wide (47'' tall x 36'' wide) area for a poster in A0 format. Poster sessions will run for one and a half hours during lunchtime. Poster authors can distribute additional materials to interested attendees at the poster session.
- One poster board is allocated to each presentation.
- Posters must be mounted using push pins provided by the organizing committee.
- Do not use foam core or any other thick/heavy material for your poster.
- Poster presenters are responsible for printing their poster and carrying or shipping it to the conference.
| Title | |
|---|---|
| 2F-1 | A 10.60 𝝁W 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection |
| 2F-2 | Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications |
| 2F-3 | Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics |
| 2F-4 | A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor |
| 2F-5 | Learned Image Codec on FPGA: Algorithm, Architecture and System Design |
| 2F-6 | Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices |
| 2F-7 | A High-Density Hybrid Buck Converter with a Charge Converging Phase Reducing Inductor Current for 12V Power Supply Systems |
| 2F-8 | A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology |
| 2F-9 | A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate |
| 2F-10 | Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection |
| 2F-11 | Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuation |
| 2F-12 | A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25–71GHz for Multi-Band 5G NR |
| 2F-13 | A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4×4 Line-of-Sight MIMO |
| 2F-14 | Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices |
| 2F-15 | Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes |
| 2F-16 | Design of 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording |
| 2F-17 | 0.36μW/channel Capacitively-coupled Chopper Instrumentation Amplifier for EEG Recording Wearable Devices with Compressed Sensing Framework |