WIP Poster Session at ASP-DAC 2025
In ASP-DAC 2025, we will host a WIP session.
Presenters provide poster presentation on their ongoing work,
with fresh problems/solutions. WIP content is typically material
that may not be mature or complete enough for full paper submission
and will not be included in the proceedings. This is an excellent
opportunity to present and discuss ongoing research with experts
from the design automation community around the world.
We strongly encourage presentations at this session from
students and young researchers from both of academics and industries.
- Date and Time: 18:00-20:00, January 21 (the end time is tentative)
- Place: Room Jupiter
| Poster ID | Title | Authors | Affiliation |
| 1 | ASiM: Improving Transparency of SRAM-based Analog Compute-in-Memory Research with an Open-Source Simulation Framework | Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Kentaro Yoshioka | Keio University (Japan) |
| 2 | Decoupling Capacitor Optimization for Power Delivery Network with a Combined Deep Learning and Genetic Algorithm | Yuchuan Lin†, Wei Xing††, Ning Xu†, Yuanqing Cheng††† | †Wuhan University of Technology (China), ††University of Sheffield (United Kingdom), †††Beihang University (China) |
| 3 | Gap Channel Routing Algorithm | Masayuki Shimoda, Atsushi Takahashi | Institute of Science Tokyo (Japan) |
| 4 | Accelerating Decision Forest Training via Node-Level Random Data Sampling | Tsukasa Yamakura, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu | Institute of Science Tokyo (Japan) |
| 5 | Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning | Ryuichi Yasuda†, Kazusa Takami†, Yuibi Gomi†, Kozo Takeuchi††, Masanori Hashimoto† | †Kyoto University (Japan), ††JAXA (Japan) |
| 6 | A Low-Cost Secure Streaming Scan Network Architecture with Test Vector Encryption | Anjum Riaz, Satyadev Ahlawat | IIT Jammu (India) |
| 7 | An evaluation of multicore RISC-V SoC performance | Nguyen The Binh, Binh Kieu-do-Nguyen, Khai-Duy Nguyen, Trong-Thuc Hoang, Cong-Kha Pham | The University of Electro-Communications (Japan) |
| 8 | Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip | Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato | Kyoto University (Japan) |
| 9 | A Lightweight On-device CNN Fine-tuning using Skip2-LoRA and Quantized Cache | Hiroki Matsutani†, Keisuke Sugiura†, Masaaki Kondo†, Radu Marculescu†† | †Keio University (Japan), ††The University of Texas at Austin (USA) |
| 10 | A Masking Method for AES Using Dynamic S-box to Resist Side-Channel Attacks | Phuc-Phan Duong, Trong-Thuc Hoang, Cong-Kha Pham | The University of Electro-Communications (Japan) |
| 11 | A Fair Resource Comparison of FPGA Implementations of Butterfly Unit for Number-Theoretic Transform without DSPs | Riku Koizumi, Daisuke Fujimoto, Yuichi Hayashi | NAIST (Japan) |
| 12 | A 20 MHz Input Frequency 4 GHz Cascade Fractional-N PLL with Multi-Phase Multi-Frequency | Thi Viet Ha Nguyen, Trong-Thuc Hoang, Cong-Kha Pham | The University of Electro-Communications (Japan) |
| 13 | Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers | Wakahiro Ohara, Takashi Sato, Hiromitsu Awano | Kyoto university (Japan) |
| 14 | 2D-QED: A Novel 2D Cross Bar Architecture for Quantum Error Decoders | Utsav Jana†, Hitesh B†, Sree Sankar E††, Masahiro Fujita†††, Binod Kumar†† | †NUS (Singapore), ††IIT Jodhpur (India), †††University of Tokyo (Japan) |
| 15 | Design Space Exploration Methodology for Chiplet-based Next-generation Heterogeneously-integrated Systems | Sakshi Thakur†, Masahiro Fujita††, Binod Kumar† | †IIT Jodhpur (India), ††University of Tokyo (Japan) |
In Cooperation with:
IEEE Council on Electronic Design Automation (CEDA) All Japan Joint Chapter
IEEE Circuits and Systems Society (CASS) Japan Joint Chapter
TOPIC:
Topic must be relevant to the ASP-DAC community.
ELIGIBILITY:
Students and young researchers are encouraged to submit, but anyone is welcome.
This session will be held in the same time of the Student Research Forum.
Those who are able to present in this session should submit.
Please note that we do not support a VISA application only to attend
this session.
PRESENTATION FORMAT:
Poster presentation in English (In-person only)
SUBMISSION:
Please submit from the submission form.
Acceptance will be judged by submitted abstract considering
the topic, the potential, and etc. Please note that the rejection
does not mean that the quality of the work is not good.
ATTENDANCE:
This session is free for attendance. Presenters and Participants
is not required the registration to ASP-DAC for this session only.
We highly recommend you register and participate in the ASP-DAC.
IMPORTANT DATES:
Submissions Deadline: Jan. 4, 2025
Date of Acceptance Notification Date: Jan. 10, 2025
ORGANIZERS:
- Chair:
- Makoto Ikeda (The University of Tokyo, Japan)
- Secretary:
- Hiromitsu Awano (Kyoto University, Japan)
CONTACT INFORMATION:
For queries, please send an e-mail to aspdac2025-wip[at]easter.kuee.kyoto-u.ac.jp.