Keynote Addresses

The venue for the keynote addresses is Cinderella Ballroom 1/6/7/8.

Opening & Keynote I : Tuesday, January 20, 08:20-09:05

Chenming Hu

TSMC Distinguished Professor Emeritus
University of California, Berkeley

Abstract:
25 years ago, the keynote speaker of the 2001 ISSCC in San Francisco projected that processor chips would dissipate more heat per area than nuclear reactor cores and rocket engine nozzles in a decade. His projection echoed the 1996 industry concensus of an end to Moore's Law in 2007 "with no known solution" (in ITRS - International Technology Rodmap of Semiconductors).
What was the cause of that chip heating crisis? How did FinFET prevent it from happening? How did FinFET find its way from the research laboratory to fabs, and the EDA/DAC and fabless communities? These and other FinFET stories will be told.

Biography:

Dr. Chenming Hu is the Emeritus TSMC Chair Professor of UC Berkeley and former CTO of TSMC. He led the creation of the BSIM standard model and the 3D transistor FinFET used in all phones, computers, data centers, and AI chips.
He received the US National Medal of Technology from President Obama and IEEE's highest honor (Medal of Honor). EDA industry's Kaufman Award cited his “tremendous career of creativity and innovation that fueled the past four decades of the semiconductor industry, including its adoption of FinFET.”

Keynote II : Tuesday, January 20, 09:05-09:50

Yiran Chen

John Cocke Distinguished Professor
Duke University

Abstract:
Edge Artificial Intelligence (Edge AI) refers to systems that execute AI models directly on devices located at or near the point of data generation. Operating locally, these interconnected systems collect and process diverse forms of data, offering distinct advantages such as enhanced privacy and reduced latency. However, deploying AI models on resource-constrained platforms remains a major challenge. Such devices are limited in computing power, memory, energy, and communication capacity, creating a gap between the demands of advanced AI models and the capabilities of current hardware—ultimately hindering the widespread adoption of Edge AI systems. In this talk, we will explore algorithmic and hardware innovations that enable Edge AI to process multimodal data efficiently and effectively (Everything), operate reliably under stringent resource constraints (Everywhere), and collaborate seamlessly across heterogeneous platforms (All at Once).

Biography:

Dr. Yiran Chen is the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University. He serves as the Principal Investigator and Director of the NSF AI Institute for Edge Computing Leveraging Next Generation Networks (Athena) and Co-Director of the Duke Center for Computational Evolutionary Intelligence (DCEI). His research group focuses on innovations in emerging memory and storage systems, machine learning and neuromorphic computing, and edge computing. Dr. Chen has authored or coauthored over 700 publications and holds 96 U.S. patents. His work has received widespread recognition, including two Test-of-Time Awards and 14 Best Paper/Poster Awards. He is the recipient of the IEEE Circuits and Systems Society's Charles A. Desoer Technical Achievement Award and the IEEE Computer Society's Edward J. McCluskey Technical Achievement Award. He also serves as the inaugural Editor-in-Chief of the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI) and the founding Chair of the IEEE Circuits and Systems Society's Machine Learning Circuits and Systems (MLCAS) Technical Committee. Dr. Chen is a Fellow of the AAAS, ACM, IEEE, and NAI, and a member of the European Academy of Sciences and Arts.

Luncheon Talk: Tuesday, January 20, 12:30-13:15

Patrick Groeneveld

Senior Fellow at AMD
Adjunct Professor, Stanford University

Abstract:
After sixty years of scaling, we've crossed a symbolic threshold: a single chip now contains more transistors than the human brain has neurons. Machines built from these devices are beginning to rival—or surpass—human intelligence. This transformation forces us to revisit a question raised at the very first Design Automation Conference in 1964: how does automation reshape our work and our society? Today, that question is more urgent than ever—not only for electronic designers but for the broader world that depends on automation. Decades of progress in Electronic Design Automation made these trillion-transistor systems possible. Synthesis, placement, and routing of billions of components—while balancing cost, performance, power, and reliability—represent one of the most intricate engineering achievements in human history.

Biography:

Dr. Patrick Groeneveld is Senior Fellow at AMD and adjunct lecturer in Stanford University's Department of Electrical Engineering. With an extensive career in Electronic Design Automation, he has held roles at both Cadence and Synopsys and served as Chief Technologist at Magma Design Automation, where he contributed to the development of a pioneering RTL-to-GDS2 synthesis tool. Patrick has also worked with AI hardware startups and held a Full Professorship in Electrical Engineering at Eindhoven University. He is the Finance Chair on the Executive Committee of the Design Automation Conference. Patrick earned his MSc and PhD degrees from Delft University of Technology in the Netherlands.

Keynote III : Wednesday, January 21, 08:20-09:05

Yuan Xie

Fang Professor of Engineering
Chair Professor, Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology

Abstract:
In this talk, the speaker reflects on a career journey marked by exploration at the intersection of technology and architecture, transitioning between academia and industry. The discussion highlights how technological advancements can drive architectural innovation, while architectural choices, in turn, influence the adoption and evolution of new technologies. Drawing from personal experience, the speaker offers a historical perspective on the dynamic interplay between 3D integration, chiplet-based design, and Processing-in-Memory (PIM) / Near-Data Processing (NDP) paradigms.

Biography:

Dr. Yuan Xie is currently with The Hong Kong University of Science and Technology as Chair Professor in ECE department and FANG Professor of Engineering. He received B.S degree in Electronic Engineering from Tsinghua University and Ph.D. degree in Computer Engineering from Princeton University. Before joining HKUST, he has rich industry experience. He was with Alibaba DAMO Academy and T-Head Semiconductor, a Professor at the University of California, Santa Barbara (UCSB), a Professor at Pennsylvania State University, with AMD Research and was with IBM Microelectronics as an Advisory Engineer. Yuan Xie is a Fellow of IEEE, ACM, and AAAS, and a recipient of many awards.

Keynote IV : Wednesday, January 21, 09:05-09:50

Charles Alpert

Cadence AI Fellow
Cadence Design Systems, Inc.

Abstract:
As the complexity of chip designs continues to escalate and design cycles shrink, the demand for enhancing designer productivity becomes imperative. Currently, designers are entrenched in manual tasks such as writing RTL, creating verification test plans, and arduously debugging physical design flows. The industry is eagerly turning to agentic AI to elevate the abstraction level for design engineers. This talk delves into how to leverage frontier models to address vexing EDA problems and outlines the challenges ahead. By harnessing the power of agentic AI, we can accelerate the design process, reduce manual effort, and optimize outcomes, meeting the growing demands of the industry.

Biography:

Dr. Charles (Chuck) Alpert is Cadence's AI Fellow and drives cross-functional Agentic AI solutions throughout Cadence's software stack. Prior to this, has led various pioneering teams in digital implementation, including Global Routing, Clock Tree Synthesis, Genus Synthesis, and Cerebrus AI. Charles has published over 100 papers and received over 100 patents in the EDA space. He is a Cadence Master inventor. He has served as Deputy-Editor-in-Chief for IEEE Transactions on Computer-Aided Design, chaired the IEEE/ACM Design Automation Conference, and earned IEEE Fellow. He received a B.S. and B.A. Degree from Stanford University and a Ph.D. in Computer Science from UCLA.

Keynote V : Thursday, January 22, 08:20-09:05

Jim Chang

TSMC Academician/Deputy Director
3DIC Design Methodology Development, TSMC

Abstract:
The era of hyper-scale AI demands a radical rethinking of 3DIC design, a paradigm shift unlocking unprecedented opportunities for architectural innovation for superior system performance. Yet, this explosion of possibility brings an exponential surge in design complexity, challenging even the most seasoned engineers.
This presentation will delve into the forefront of this revolution. We begin with a review of the TSMC 3DFabric™ family of solutions, specifically engineered to power the most advanced AI systems on the market today. We will then pivot to a comprehensive exploration of the critical 3DIC design challenges that emerge at this bleeding edge: from intricate 3D integration and feasibility assessment to robust implementation, power integrity, physical verification, thermal analysis, and substrate design optimization.
Join us to discover how a cohesive suite of solutions is forming the foundation for designing the AI systems of tomorrow - systems that will redefine what's possible. This is your essential guide to conquering complexity and harnessing the full potential of 3DIC for the next generation of intelligent machines.

Biography:

Dr. Jim Chang leads the 3DIC design methodology development efforts in TSMC. With over two decades of semiconductor experience, Jim is a recognized expert in synthesis, physical optimization, detailed routing, and timing analysis. Prior to his current role, he spearheaded TSMC's design flow development and EDA certification program for advanced 7nm to 3nm technology nodes. His extensive background also includes R&D leadership positions at prominent EDA companies such as Plato, Cadence, Extreme DA, and Synopsys. Dr. Chang holds a Ph.D. in Electrical and Computer Engineering from the University of California, Santa Barbara.

Keynote VI : Thursday, January 22, 09:05-09:50

Takefumi Miyoshi

Director at e-trees.Japan, Inc.
Adjunct Professor, The University of Osaka
Founder, QuEL, Inc.

Abstract:
Quantum computing has advanced rapidly in recent years, raising strong expectations for its transformative impact on information processing. As quantum processors scale in size and complexity, progress in their control systems becomes increasingly essential.
This talk first introduces the roles of control systems in quantum computing and then presents our efforts in developing scalable and precise quantum computer controllers featuring high-accuracy microwave transceivers and synchronization mechanisms for reliable qubit manipulation and measurement. As we approach fault-tolerant quantum computing (FTQC), the scalability and efficiency of control electronics emerge as major challenges.
To address these challenges, compact, high-performance, and energy-efficient LSI-based control systems are required, supported by advanced design methodologies and electronic design automation (EDA) tools. Promising directions such as cryogenic CMOS integration may also open new possibilities for co-design between quantum and classical electronics. The talk will highlight how innovations in digital and analog integrated circuit design and system integration can accelerate the realization of large-scale quantum computing.

Biography:

Dr. Takefumi Miyoshi received his Ph.D. from the Interdisciplinary Graduate School of Science and Engineering at Tokyo Institute of Technology in 2007. He is a Director at e-trees.Japan, Inc. and an Adjunct Professor at the Center for Quantum Information and Quantum Biology at The University of Osaka. Dr. Miyoshi is also one of the founders of QuEL, Inc., where he works as the CTO. His research interests include reconfigurable system, computer architecture, compiler, and quantum computing.

Last Updated on: November 04, 2025