Tutorials

ASP-DAC 2026 offers attendees a set of 3 hours intense introductions to specific topics. If you register for the conference, you have the option to select two out of the six topics.

  • Date: Monday, January 19, 2026 (9:00 — 17:00)
Sleeping Beauty
1/2		 Sleeping Beauty
3		 Sleeping Beauty
5
09:00 — 12:00 Tutorial-1
On-Device AI to Better Mobile and Implantable Devices in Healthcare		 Tutorial-2
Design Methodologies and Toolchains for Compute-in-Memory: From Architectures to Systems		 Tutorial-3
Design Automation for the Early Fault Tolerant Quantum Computing
14:00 — 17:00 Tutorial-4
Bi-Directional Synergy: A Tutorial on Hardware Design for Agentic AI and Agentic AI for Hardware Design		 Tutorial-5
APS: An MLIR-Based Hardware-Software Co-design Framework for Agile Processor Specialization		 Tutorial-6
Post-Silicon Validation & Hardware Security in Modern Processors

Tutorial-1: Monday, January 19, 9:00—12:00
@ Sleeping Beauty 1/2

On-Device AI to Better Mobile and Implantable Devices in Healthcare

Speaker(s):
Yiyu Shi (University of Notre Dame)

Abstract: The increasing prevalence of chronic diseases, an aging population, and a shortage of healthcare professionals have prompted the widespread adoption of mobile and implantable devices to effectively manage various health conditions. In recent years, there is growing interest in leveraging rapid advances in artificial intelligence (AI) to enhance the performance of these devices, resulting in better patient outcomes, reduced healthcare costs, and improved patient autonomy. Due to privacy, security, and safety considerations, inferences must often be performed on the edge, with limited hardware resources. This challenge is compounded by inter-patient and intra-patient variability, heavy dependence on medical domain knowledge, and lack of diversified training data.
In this tutorial, we will explore how hardware–AI co-design techniques, such as joint hardware and neural architecture optimization and fairness-aware pruning, can fundamentally transform mobile and implantable devices. We will share case studies, including the world’s first smart Implantable Cardioverter Defibrillator (ICD) enabled by our research, illustrating how advanced edge AI methodologies can make these devices safer, more efficient, and more personalized. Attendees will gain actionable insights into deploying AI models under stringent constraints while addressing fairness, adaptability, and reliability challenges unique to healthcare applications.

Biographies: Dr. Yiyu Shi currently a professor in the Department of Computer Science and Engineering at the University of Notre Dame, a visiting scientist at Boston Children’s Hospital and Havard Medical School, the site director of National Science Foundation I/UCRC Alternative and Sustainable Intelligent Computing, and the director of the Sustainable Computing Lab (SCL). He received his B.S. in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively. His current research interests focus on hardware intelligence and biomedical applications, with close to a dozen publications in Nature and Science research journals such as Nature Machine Intelligence, Nature Intelligence and Nature Communications . In recognition of his research, more than a dozen of his papers have been nominated for or awarded as the best paper in top journals and conferences, including the 2023 ACM/IEEE William J. McCalla ICCAD Best Paper Award and 2021 IEEE Transactions on Computer-Aided Design Donald O Pederson Best Paper Award. He is also the recipient of Facebook Research Award, IBM Invention Achievement Award, NSF CAREER Award, IEEE Region 5 Outstanding Individual Achievement Award, IEEE Computer Society Mid-Career Research Achievement Award, among others. He has served on the technical program committee of many international conferences. He is the deputy editor-in-chief of IEEE VLSI CAS Newsletter, and an associate editor of various IEEE and ACM journals. He is an IEEE CEDA distinguished lecturer and an ACM distinguished speaker.


Tutorial-2: Monday, January 19, 9:00—12:00
@ Sleeping Beauty 3

Design Methodologies and Toolchains for Compute-in-Memory: From Architectures to Systems

Speaker(s):
Xiaoming Chen (Institute of Computing Technology, Chinese Academy of Sciences)
Jianlei Yang (Beihang University)
Zhenhua Zhu (Tsinghua University)

Abstract: As the demand for computational efficiency in modern AI applications continues to rise, Compute-in-Memory (CIM) has emerged as a promising computation paradigm. By performing computations directly within memory arrays, CIM architectures overcome the von-Neumann bottleneck within traditional architectures. While recent CIM hardware designs have demonstrated impressive efficiency gains for neural network workloads, architectural innovation has significantly outpaced the development of cohesive software toolchains necessary to program, optimize, and evaluate these novel architectures.
This tutorial addresses a critical gap in system-level CIM design by presenting comprehensive design methodologies and software frameworks, which bridge the divide between algorithm development and hardware implementation. Specifically, it aims to:
  ☆ Introduce the fundamentals of CIM design and analyze the algorithmic and architectural design space for CIM systems.
  ☆ Present state-of-the-art open-source frameworks that enable end-to-end design, simulation, compilation, and evaluation.
  ☆ Demonstrate practical workflows for algorithm mapping, performance modeling, and hardware-aware optimization.
Through detailed examination of existing design tools, intuitive examples, and hands-on demonstrations, this tutorial will offer attendees an opportunity to gain comprehensive insights into the current landscape of CIM design automation and methodologies that are essential for developing efficient AI accelerators.

Biographies:

Xiaoming Chen (Institute of Computing Technology, Chinese Academy of Sciences)
Xiaoming Chen is now a Professor with Institute of Computing Technology, Chinese Academy of Sciences. He received the BS and PhD degrees in electronic engineering from Tsinghua University, Beijing, China, in 2009 and 2014, respectively. His current research interests include design automation for integrated circuits and computer architectures. He has published more than 140 papers in DAC, ICCAD, HPCA, MICRO, ASPLOS, IEEE TCAD, IEEE TC, etc. His researches have been adopted by commercial EDA software. He was a recipient of the NSFC Excellent Young Scientists Fund, 2016 European Design and Automation Association (EDAA) Outstanding Dissertation Award (the sole awardee from Chinese Mainland doctors till now), 2018 DAMO Academy Young Fellow Award, and ASP-DAC 2022 Best Paper Award.
Jianlei Yang (Beihang University)
Jianlei Yang is currently a Professor in the School of Computer Science and Engineering at Beihang University, China. He received his Ph.D. degree in Computer Science and Technology from Tsinghua University in 2014. From 2014 to 2016, he was a postdoctoral researcher with the Department of ECE at the University of Pittsburgh. His current research interests include ML/LLM systems, computer architectures, and Compute-in-Memory. He has published over 100 papers in DAC, ICCAD, ISCA, KDD, AAAI, and IEEE TCAD, IEEE TC, etc. He has received several notable awards including the IEEE ICCD Best Paper Award (2013), ACM GLSVLSI Best Paper Nomination (2015), IEEE ICESS Best Paper Award (2017), and ACM SIGKDD Best Student Paper Award (2020). He is a senior member of IEEE and CCF, and has served as PIM Track Co-Chair for DAC 2022 and CAD Track Chair for GLSVLSI 2018/2019.
Zhenhua Zhu (Tsinghua University)
Zhenhua Zhu received his B.S. and Ph.D. (with honor) degrees from the Department of Electronic Engineering, Tsinghua University, China, in 2018 and 2024. Currently, he is serving as a postdoc researcher in the Department of EE, Tsinghua University and a visiting scholar in the Department of ECE, HKUST. He has been devoted to the research of Computing-In-Memory, Near-Memory Computing, etc. He has published 40 academic papers in IEEE TCAD, DAC, ISCA, MICRO, ICCAD, ASPLOS, and DATE, with Google Scholar citations more than 1,300. He has proposed the behavioral-level simulator MNSIM, the hardware-software co-optimization tool Gibbon, and the unified compiler UniNDP for CIM systems. His related work received the Best Paper Honorable Mention Award in HPCA 2025 and the Best Paper Nomination in DATE 2023.


Tutorial-3: Monday, January 19, 9:00—12:00
@ Sleeping Beauty 5

Design Automation for the Early Fault Tolerant Quantum Computing

Speaker(s):
Shigeru Yamashita (Ritsumeikan University)
He Li (Southeast University)
Zhiding Liang (CUHK)
Robert Wille (Technical University of Munich)

Abstract: As quantum computing transitions from NISQ experimentation to the early fault-tolerant (Early FTQC) era, progress hinges on crosslayer methods that can solve critical design automation challenges. Success in Early FTQC will require (i) reducing expensive non-Clifford resources (T-count/T-depth), (ii) co-designing algorithms and ansätze with problem structure and hardware constraints, and (iii) sustaining low physical error rates through scalable, hardware-aware calibration. This tutorial brings together four complementary perspectives to address these needs. We will explore T-depth-aware decomposition for MCT-intensive oracles, application-driven algorithm/ansatz co-design using contextual subspace strategies, and fine-grained, graph-parallel calibration protocols validated on real devices. Finally, we will present a unifying design-automation (QDA) view that connects today’s tools to the emerging requirements of Early FTQC. Attendees will leave with concrete techniques, open-source pointers, and evaluation checklists to apply immediately in their research and development.

Biographies:

Shigeru Yamashita (Ritsumeikan University)
Shigeru Yamashita received the B.E., M.E., and Ph.D. degrees in information science from Kyoto University, Kyoto, Japan, in 1993, 1995, and 2001, respectively. In 1995, he joined NTT Communication Science Laboratories, Kyoto, where he engaged in research of computer-aided design of digital systems and new type of computer architectures. He is a Professor with the College of Information Science and Engineering, Ritsumeikan University, Shiga, Japan. From 2000 to 2003, he was also a Researcher with Quantum Computation and Information, ERATO, Japan Science and Technology Corporation, Tokyo, Japan. From 2003 to 2009, he was an Associate Professor with the Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Japan. He also served as a Visiting Professor with the National Institute of Informatics, Tokyo, from 2012 to 2017. Prof. Yamashita received the 2000 IEEE Circuits and Systems Society Transactions on Computer-Aided Design of Integrated Circuits and Systems Best Paper Award, the SASIMI 2010 Best Paper Award, the 2010 IPSJ Yamashita SIG Research Award, the SASIMI 2018 Outstanding Paper Award, the SASIMI 2022 Outstanding Paper Award, and the Marubun Academic Achievement Award of the Marubun Research Promotion Foundation. He is a Senior Member of IEICE and a member of ACM and IPSJ.
He Li (Southeast University)
He Li received the Ph.D. degree with Imperial College London, London, U.K., in 2020. He is a Professor, Head of Circuits and Systems Department, and Head of Heterogeneous Intelligent and Quantum Computing (HIQC) Lab, the School of Electronic Science and Engineering, Southeast University, Nanjing, China. Before joining Southeast, he was a Research Associate with the University of Cambridge, and a teaching staff with Trinity College Cambridge, Cambridge, U.K. He serves on technical program committees of the top-tier EDA and reconfigurable computing conferences (DAC, ICCAD, DATE, FCCM, FPL, FPT, ASP-DAC, ASAP, etc.). He also serves as an Organization Committee Member for multiple IEEE/ACM international conferences. Dr. Li was the IEEE FPT’17 best paper presentation award recipient and ACM MLCAD’24 best paper nominee.
Zhiding Liang (CUHK)
Zhiding Liang is an assistant professor at the CUHK CSE. He was an assistant professor at Rensselaer Polytechnic Institute (RPI) CS department from 2024 - 2025. He received PhD degree from the University of Notre Dame at 2024. The results of his research have been published in prestigious conferences and journals, including ISCA, DAC, ICCAD, QCE, SIGMETRICS, TCAD, TSG, TQE, and TVCG. He has been selected as a DAC Young Fellow in both 2021 and 2022, the ML and Systems Rising Star at 2025. He has also been nominated as the recipient of the Edison Innovation Fellowship by the IDEA Center at the University of Notre Dame. He is devoted to quantum education and outreach; he is the cofounder of the Quantum Computer System (QuCS) Lecture Series, an impactful public online lecture series in the quantum computing community. He is one of the major contributors to the TorchQuantum library, which has been adopted by IBM Qiskit Ecosystem and PyTorch Ecosystem with 1.3K+ stars on GitHub.
Robert Wille (Technical University of Munich)
Robert Wille is a full and distinguished professor at the Technical University of Munich, CEO of the Munich Quantum Software Company (MQSC), and scientific director at the Software Competence Center Hagenberg. He received his diploma and Dr.-Ing. degrees in computer science from the University of Bremen in 2006 and 2009, respectively. His academic journey includes positions at the University of Bremen, DFKI, the University of Potsdam, TU Dresden, and JKU Linz. Robert’s research focuses on circuit and system design for conventional and emerging technologies. For over 15 years, he has advanced quantum computing — establishing foundational software and design automation concepts. His work has earned Best Paper awards, the DAC Under-40 Innovators Award, a Google Research Award, an ERC Consolidator Grant, and more. He serves on numerous boards, plays a key role in the Munich Quantum Valley, has published 400+ papers, and engages in technology transfer from research to practice.


Tutorial-4: Monday, January 19, 14:00—17:00
@ Sleeping Beauty 1/2

Bi-Directional Synergy: A Tutorial on Hardware Design for Agentic AI and Agentic AI for Hardware Design

Speaker(s):
Chaojian Li (Hong Kong University of Science and Technology)
Zhongzhi Yu (NVIDIA Research)
Zhiyao Xie (Hong Kong University of Science and Technology)

Abstract: Agentic AI systems, capable of reasoning, planning, and autonomous decision-making, are transforming how we design and deploy both AI algorithms and hardware systems. This tutorial focuses on the bi-directional synergy between hardware design for agentic AI and agentic AI for hardware design. We will cover three representative works: (1) ORCHES, which accelerates Large Language Model (LLM) reasoning for agentic AI using collaborative GPU–Processing-In-Memory(PIM) heterogeneous architectures, (2) Spec2RTL-Agent, an LLM-agent system that automates RTL code generation from complex design specifications, and (3) SLM-Agents, which makes the case that Small Language Models (SLMs) will be the future of agentic AI because of their efficiency and scalability. Participants will gain insights into (1) hardware challenges and opportunities in supporting reasoning-centric agentic AI applications, (2) LLM-based multi-agent workflows that can revolutionize hardware design automation, and (3) the significance of SLMs in shaping efficient and sustainable agentic AI systems. The tutorial concludes with a discussion on how hardware design and agentic AI can together drive a virtuous cycle of progress.

Biographies:

Chaojian Li (Hong Kong University of Science and Technology)
Dr. Chaojian Li is an Assistant Professor in the Department of Computer Science and Engineering at the Hong Kong University of Science and Technology, where he leads the Sponge Computing Lab. He received his Ph.D. in Computer Science from Georgia Institute of Technology in 2025, advised by Prof. Yingyan (Celine) Lin. His research lies at the intersection of deep learning, computer architecture, and efficient AI systems, with a focus on co-design for large language models and 3D intelligence. His research contributions have been recognized with several prestigious honors, including the Best Paper Award at MICRO 2024, selection as an MLCommons ML and Systems Rising Star, 1st Place in the Ph.D. Forum at DAC 2024, and 1st Place in the TinyML Design Contest at ICCAD 2022.
Zhongzhi Yu (NVIDIA Research)
Dr. Zhongzhi Yu is a Research Scientist at NVIDIA Research, specializing in LLM for hardware design and LLM efficiency. He obtained his Ph.D. in Computer Science from the Georgia Institute of Technology in 2025, advised by Prof. Yingyan (Celine) Lin. His research focuses on enabling effective adaptation of foundation models to downstream tasks that require extensive domain knowledge, such as hardware design, as well as designing efficient inference and tuning methods for foundation models. His research contributions have been recognized with several honors, including the Best Paper Award at the IEEE International Workshop on LLM-Aided Design 2024 and the 2nd Place Best Demo Award at DAC 2023.
Zhiyao Xie (Hong Kong University of Science and Technology)
Dr. Zhiyao Xie is an Assistant Professor in the ECE Department at Hong Kong University of Science and Technology (HKUST) since 2022. His research focuses on AI-assisted electronic design automation (EDA) and chip design methodologies. He completed his Ph.D. at Duke University in 2022 under the supervision of Prof. Yiran Chen and Prof. Hai (Helen) Li, following his B.Eng from CityU HK in 2017 with a full scholarship & first-class honours. During his Ph.D. studies, Zhiyao also worked as a research intern at leading IC and EDA companies, including NVIDIA, Arm, Cadence, and Synopsys, where he was fortunate to work with Dr. Haoxing (Mark) Ren, Dr. Brucek Khailany, Dr. Xiaoqing Xu, Dr. Shidhartha Das, and Prof. Jiang Hu. Zhiyao has received multiple prestigious awards, including the RGC HK Early Career Award 2023 (7 out of 525 HK faculty), ACM Outstanding Dissertation Award in EDA 2023 (1 awardee worldwide per year), EDAA Outstanding Dissertation Award 2023 (4 awardees worldwide per year), MICRO 2021 Best Paper Award (1st-author, 1 out of 430), ASP-DAC 2023 Best Paper Award (2 out of 328), WAIC Yufan Award (Brilliant Star) 2023, ACM SIGDA SRF 2022 Best Research Poster Award, and 4 more best paper nominations. He also received Faculty Teaching Excellence Appreciation Award 2023/24 for his computer architecture course. He has published 50+ refereed papers, more than half in top EDA venues (DAC, ICCAD, IEEE TCAD) and some others in top computer architecture venues (MICRO, ISCA, HPCA).


Tutorial-5: Monday, January 19, 14:00—17:00
@ Sleeping Beauty 3

APS: An MLIR-Based Hardware-Software Co-design Framework for Agile Processor Specialization

Speaker(s):
Yun (Eric) Liang (Peking University)
Youwei Xiao (Peking University)
Yuyang Zou (Peking University)

Abstract: The rapid evolution of domain-specific applications demands specialized processors with competitive performance and efficiency. While the open RISC-V instruction set architecture (ISA) simplifies the adoption of custom instruction extensions (ISAXs), the overall process of processor specialization remains challenging. It involves a complex interplay of multiple tasks, including behavioral architecture description, hardware synthesis and implementation, processor-ISAX adaptation, and compiler co-generation. Existing RISC-V ecosystems often address these challenges manually, lacking a fully automated and integrated solution. This tutorial introduces APS for agile processor specialization based on Multi-Level Intermediate Representation (MLIR). MLIR can support multiple different requirements in a unified infrastructure. APS provides a unified framework of powerful, open-source EDA tools for seamless hardware-software co-design, empowering designers to navigate the complexities of specialization with greater ease and efficiency.

Biographies:

Yun (Eric) Liang (Peking University)
Prof Yun (Eric) Liang is currently an Endowed Boya Distinguished Professor in the School of Integrated Circuit and EECS at Peking University. His research interest is at the hardware-software interface with work spanning electronic design automation (EDA), hardware and software co-design, and reconfigurable computing. He currently serves as Associate Editor of the ACM Transactions on Embedded Computing Systems (TECS) and ACM Transactions on Reconfigurable Technology and Systems (TRETS). He was the program chair of 30th Annual IEEE International Conference on Application-specific Systems, Architecture and Processors (ASAP) 2019 and the International Conference on Field Programmable Technology (FPT) 2022. He currently serves in the program committees in the premier conferences including DAC, ICCAD, FPGA, FCCM, HPCA, MICRO, ASPDAC, etc. He also served as special session organizer, exhibition chair, subcommittee chair, and best paper selection committee for ASPDAC.
Youwei Xiao (Peking University)
Mr. Youwei Xiao is a fourth-year PhD student at Peking University, China. His research interests include agile hardware design and compiler optimization.

Yuyang Zou (Peking University)
Mr. Yuyang Zou is a first-year Master student at Peking University. His research interests include FPGA and agile processor specialization.
Prof Yun Liang will present the Background Session and Youwei Xiao and Yuyang Zou will present the Hands-on Session.


Tutorial-6: Monday, January 19, 14:00—17:00
@ Sleeping Beauty 5

Post-Silicon Validation & Hardware Security in Modern Processors

Speaker(s):
Ravi Monani (Senior System Design Engineer, AMD; former Intel)

Abstract: Modern processors face a dual challenge: achieving peak performance while ensuring robust security and reliability. With increasing complexity in CPU/GPU/SoC architectures, post-silicon validation has become critical in detecting design flaws, mitigating microarchitectural vulnerabilities, and balancing power-performance tradeoffs. This tutorial provides a practitioner’s perspective, drawing on experiences from AMD and Intel, to bridge the gap between academic research and industrial practice. Topics will include silicon bring-up methodologies, case studies of hardware security vulnerabilities (e.g., speculative execution, side-channel attacks), debug and measurement techniques, and future challenges in secure processor design. Participants will gain insights into practical validation flows, security-hardening strategies, and opportunities for research collaboration with industry.

Biographies:

Ravi Monani (Senior System Design Engineer, AMD; former Intel)
Ravi Monani is a Senior System Design Engineer at AMD, with prior engineering experience at Intel. His professional expertise includes post-silicon validation, hardware security, CPU/GPU microarchitecture, SoC bring-up, power-performance tuning, and reliability analysis. He has contributed to industry-recognized hardware security mitigations (covering speculative execution and side-channel vulnerabilities), high-performance CPU/GPU bring-up projects, and silicon debug methodologies. Ravi has published in IEEE/ACM venues, received multiple corporate awards, and served as a reviewer for IEEE journals and international conferences. His academic research explores chaos-based encryption and non-linear dynamical systems for secure IoT hardware. Combining research and industry perspectives, Ravi brings practical insights on how validation, debug, and security-hardened designs shape modern processor reliability.


Last Updated on: October 09, 2025