SESSION: Keynote address

• Rajeev Madhavan,"Silicon compilation: the answer to reducing IC development costs," Pages: 1 - 2
• Jan M. Rabaey,"Design at the end of the silicon roadmap," Pages: 1 - 2
• Zhenghua Jiang,"The development of integrated circuit industry in China," Pages: 1 - 2

SESSION: Tree construction and buffering

• Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan,"The polygonal contraction heuristic for rectilinear Steiner tree construction," Pages: 1 - 6
• Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan,"An-OARSMan: obstacle-avoiding routing tree construction with good length performance," Pages: 7 - 12
• Zhuo Li, C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi,"Making fast buffer insertion even faster via approximation techniques," Pages: 13 - 18
• Zhong-Ching Lu, Ting-Chi Wang,"Concurrent flip-flop and buffer insertion with adaptive blockage avoidance," Pages: 19 - 22
• Tianpei Zhang, Sachin S. Sapatnekar,"Buffering global interconnects in structured ASIC design," Pages: 23 - 26

SESSION: System level design methodology for network-on-chip

• Srinivasan Murali, Luca Benini, Giovanni De Micheli,"Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees," Pages: 27 - 32
• Cesar Marcon, Andre Borin, Altamiro Susin, Luigi Carro, Flavio Wagner,"Time and energy efficient mapping of embedded applications onto NoCs," Pages: 33 - 38
• Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou,"Communication-driven task binding for multiprocessor with latency insensitive network-on-chip," Pages: 39 - 44
• Andreas Gerstlauer, Dongwan Shin, Rainer Domer, Daniel D. Gajski,"System-level communication modeling for network-on-chip synthesis," Pages: 45 - 48
• Luciano Ost, Aline Mello, Jose Palma, Fernando Moraes, Ney Calazans,"MAIA: a framework for networks on chip generation and verification," Pages: 49 - 52

SESSION: Test and DFT (1)

• Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li,"Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code," Pages: 53 - 58
• Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty,"Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation," Pages: 59 - 64
• Jin-Fu Li,"Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs," Pages: 65 - 70
• Feng Shi, Yiorgos Makris,"SPIN-PAC: test compaction for speed-independent circuits," Pages: 71 - 74
• Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue,"A Huffman-based coding with efficient test application," Pages: 75 - 78

SESSION: (Special session) DFM

• Vijay Pitchumani,"Embedded tutorial I: design for manufacturability," Pages: 1 - 1
• Rouying Zhan, Haolu Xie, Haigang Feng, Albert Wang,"ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress," Pages: 79 - 82
• Xiaolang Yan, Ye Chen, Zheng Shi, Yue Ma,"A new method for model based frugal OPC," Pages: 83 - 86

SESSION: Clock, power grid and thermal analysis and optimization

• Yong Zhan, Sachin S. Sapatnekar,"Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up," Pages: 87 - 92
• Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan,"Analysis of buffered hybrid structured clock networks," Pages: 93 - 98
• Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu,"Clock network minimization methodology based on incremental placement," Pages: 99 - 102
• Hongyu Chen, Chung-Kuan Cheng,"A multi-level transmission line network approach for multi-giga hertz clock distribution," Pages: 103 - 106
• Zhixin Tian, Huazhong Yang, Rong Luo,"Gibbs sampling in power grid analysis," Pages: 107 - 110
• Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan,"A wideband hierarchical circuit reduction for massively coupled interconnects," Pages: 111 - 114

SESSION: Routing and interconnects

• Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He,"A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem," Pages: 115 - 120
• Jason Cong, Yan Zhang,"Thermal-driven multilevel routing for 3-D ICs," Pages: 121 - 126
• Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen,"Wave-pipelined on-chip global interconnect," Pages: 127 - 132
• Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu,"Evaluation of on-chip transmission line interconnect using wire length distribution," Pages: 133 - 138

SESSION: System level modeling and embedded software

• Samar Abdi, Daniel Gajski,"A formalism for functionality preserving system level transformations," Pages: 139 - 144
• KiSeun Kwon, YoungMin Yi, DoHyung Kim, SoonHoi Ha,"Embedded software generation from system level specification for multi-tasking embedded systems," Pages: 145 - 150
• Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya,"Scheduler implementation in MP SoC design," Pages: 151 - 156
• G. Chen, M. Kandemir,"Optimizing embedded applications using programmer-inserted hints," Pages: 157 - 160
• Dohyung Kim, Soonhoi Ha,"Static analysis and automatic code synthesis of flexible FSM model," Pages: 161 - 165

SESSION: Test and DFT (2)

• Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng,"Constraint extraction for pseudo-functional scan-based delay testing," Pages: 166 - 171
• Hafizur Rahaman, Debesh K. Das,"Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA," Pages: 172 - 177
• Xijiang Lin, Janusz Rajski,"Propagation delay fault: a new fault model to test delay faults," Pages: 178 - 183
• Katherine Shu-Min Li, Chung Len Lee, Chauchin Su, Jwu E Chen,"Oscillation ring based interconnect test scheme for SOC," Pages: 184 - 187
• Junhao Shi, Gorschwin Fey, Rolf Drechsler,"Bridging fault testability of BDD circuits," Pages: 188 - 191

SESSION: TCAD

• Debjit Sinha, Hai Zhou,"Yield driven gate sizing for coupling-noise reduction under uncertainty," Pages: 192 - 197
• Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang,"Maze routing with OPC consideration," Pages: 198 - 203
• Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi,"Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm," Pages: 204 - 207
• Xiren Wang, Wenjian Yu, Zeyi Wang,"Substrate resistance extraction with direct boundary element method," Pages: 208 - 211
• Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Wang,"An efficient combinationality check technique for the synthesis of cyclic combinational circuits," Pages: 212 - 215
• Ke Cao, Puneet Dhawan, Jiang Hu,"Library cell layout with Alt-PSM compliance and composability," Pages: 216 - 219
• Rasit Onur Topaloglu, Alex Orailoglu,"Forward discrete probability propagation method for device performance characterization under process variations," Pages: 220 - 223

SESSION: Simulation and modeling techniques for RF/analog circuits

• Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He,"Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction," Pages: 224 - 229
• Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Geoges Gielen,"Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams," Pages: 230 - 235
• Xiaochun Duan, Kartikeya Mayaram,"A new approach for ring oscillator simulation using the harmonic balance method," Pages: 236 - 239
• Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh,"Efficient transient simulation for transistor-level analysis," Pages: 240 - 243
• Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou,"Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits," Pages: 244 - 249
• Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen,"Block based statistical timing analysis with extended canonical timing model," Pages: 250 - 253

SESSION: Logic synthesis

• Lin Yuan, Gang Qu, Tiziano Villa, Alberto Sangiovanni-Vincentelli,"FSM re-engineering and its application in low power state encoding," Pages: 254 - 259
• Aiqun Cao, Ruibing Lu, Cheng-Kok Koh,"Post-layout logic duplication for synthesis of domino circuits with complex gates," Pages: 260 - 265
• Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch,"Detecting support-reducing bound sets using two-cofactor symmetries," Pages: 266 - 271
• Vivek V. Shende, Stephen S. Bullock, Igor L. Markov,"Synthesis of quantum logic circuits," Pages: 272 - 275
• Stephen Plaza, Valeria Bertacco,"STACCATO: disjoint support decompositions from BDDs through symbolic kernels," Pages: 276 - 279

SESSION: System level architecture design

• Oliver Schliebusch, A. Chattopadhyay, D. Kammler, G. Ascheid, R. Leupers, H. Meyr, Tim Kogel,"A framework for automated and optimized ASIP implementation supporting multiple hardware description languages," Pages: 280 - 285
• Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki,"A processor core synthesis system in IP-based SoC design," Pages: 286 - 291
• Koushik Niyogi, Diana Marculescu,"Speed and voltage selection for GALS systems based on voltage/frequency islands," Pages: 292 - 297
• Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jurgen Teich,"A system-level approach to hardware reconfigurable systems," Pages: 298 - 301
• Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin H.-M. Sha,"High-level synthesis for DSP applications using heterogeneous functional units," Pages: 302 - 304

SESSION: Test and verification

• Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara,"Evaluation of the statistical delay quality model," Pages: 305 - 310
• Wenjing Rao, Alex Orailoglu, Ramesh Karri,"Fault tolerant nanoelectronic processor architectures," Pages: 311 - 316
• Shireesh Verma, Kiran Ramineni, Ian G. Harris,"An efficient control-oriented coverage metric," Pages: 317 - 322
• Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou,"An observability measure to enhance statement coverage metric for proper evaluation of verification completeness," Pages: 323 - 326
• Jin Yang, Avi Puder,"Tightly integrate dynamic verification with formal verification: a GSTE based approach," Pages: 327 - 330

SESSION: Special session

• C. K. Cheng, Steve Lin, Andrew Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen,"Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?," Pages: 1 - 1

SESSION: Placement techniques

• Satoshi Ono, Patrick H. Madden,"On structure and suboptimality in placement," Pages: 331 - 336
• Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi Ono, Purushothaman Damodaran, Krishnaswami Srihari, Patrick H. Madden,"Optimal placement by branch-and-price," Pages: 337 - 342
• Puneet Gupta, Andrew B. Kahng, Chul-Hong Park,"Detailed placement for improved depth of focus and CD control," Pages: 343 - 348
• Chen Li, Cheng-Kok Koh, Patrick H. Madden,"Floorplan management: incremental placement for gate sizing and buffer insertion," Pages: 349 - 354

SESSION: Security processor design

• Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu,"Low-power techniques for network security processors," Pages: 355 - 360
• Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu,"A configurable AES processor for enhanced security," Pages: 361 - 366
• Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang,"Power estimation starategies for a low-power security processor," Pages: 367 - 371
• Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu,"Design and test of a scalable security processor," Pages: 372 - 375
• Yung Chia Lin, Chung Wen Huang, Jenq Kuen Lee,"System-level design space exploration for security processor prototyping in analytical approaches," Pages: 376 - 380

SESSION: (Special session) embedded tutorial II

• David Blaauw, Anirudh Devgan, Farid Najm,"Leakage power: trends, analysis and avoidance," Pages: 1 - 1

SESSION: (Special session) CAD for microarchitecture designs

• Bill Grundmann,"Challenges to covering the high-level to silicon gap," Pages: 1 - 1
• Todd Austin, Valeria Bertacco, David Blaauw, Trevor Mudge,"Opportunities and challenges for better than worst-case design," Pages: 2 - 7
• Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong,"Microarchitecture evaluation with floorplanning and interconnect pipelining," Pages: 8 - 15

SESSION: University design contest

• Hongxia Wang, Samuel Rodriguez, Cagdas Dirik, Amol Gole, Vincent Chan, Bruce Jacob,"TERPS: the embedded reliable processing system," Pages: 1 - 2
• D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, A. Thanailakis,"AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow," Pages: 3 - 4
• Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao,"Standard CMOS technology on-chip inductors with pn junctions substrate isolation," Pages: 5 - 6
• Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang,"A bandwidth efficient subsampling-based block matching architecture for motion estimation," Pages: 7 - 8
• Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera,"Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18ƒÊm CMOS process," Pages: 9 - 10
• Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li,"A design of high speed double precision floating point adder using macro modules," Pages: 11 - 12
• Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jurgen Mattausch,"A low-power video segmentation LSI with boundary-active-only architecture," Pages: 13 - 14
• Xu Ningyi, Li Shaohua, Yu Wei, He Guanghui, Zhang Hao, Luo Fei, Zhou Zucheng,"The design and implementation of a DVB receiving chip with PCI interface," Pages: 15 - 16
• De_Hui Zhang, Quan_Liang Zhao, Jun-Gang Han,"Design and implementation of an SDH high-speed switch," Pages: 17 - 18
• Arias Tanti Hapsari, Eniman Y Syamsudin, Imron Pramana,"Design of vehicle position tracking system using short message services and its implementation on FPGA," Pages: 19 - 20
• Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun,"Design of A 2.4-GHz integrated frequency synthesizer," Pages: 21 - 22
• Feng Jianhua, Long Jieyi, Xu Wenhua, Ye Hongfei,"An improved test access mechanism structure and optimization technique in system-on-chip," Pages: 23 - 24

SESSION: (Special session) embedded tutorial III

• Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin,"Designing reliable circuit in the presence of soft errors," Pages: 1 - 1

SESSION: Design optimization for high-performance digital circuits

• Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen,"Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation," Pages: 381 - 386
• Zhaojun Wo, Israel Koren,"Effective analytical delay model for transistor sizing," Pages: 387 - 392
• Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan,"Achieving continuous VT performance in a dual VT process," Pages: 393 - 398
• Dongwoo Lee, David Blaauw, Dennis Sylvester,"Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment," Pages: 399 - 404

SESSION: Floorplanning and partitioning

• Lei Cheng, Liang Deng, Martin D. F. Wong,"Floorplanning for 3-D VLSI design," Pages: 405 - 411
• Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong,"Optimal redistribution of white space for wire length minimization," Pages: 412 - 417
• Yongseok Cheon, Martin D. F. Wong,"Crowdedness-balanced multilevel partitioning for uniform resource utilization," Pages: 418 - 423
• Ramprasad Ravichandran, Mike Niemier, Sung Kyu Lim,"Partitioning and placement for buildable QCA circuits," Pages: 424 - 427
• Chanseok Hwang, Massoud Pedram,"PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits," Pages: 428 - 431

SESSION: Advances in SAT technology and application

• Jinbo Huang,"MUP: a minimal unsatisfiability prover," Pages: 432 - 437
• Domagoj Babi?, Alan J. Hu,"Integration of supercubing and learning in a SAT solver," Pages: 438 - 444
• Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah,"Dynamic symmetry-breaking for improved Boolean optimization," Pages: 445 - 450
• Shengyu Shen, Ying Qin, SiKun Li,"A fast counterexample minimization approach with refutation analysis and incremental SAT," Pages: 451 - 454
• Wei Huang, PuShan Tang, Min Ding,"Sequential equivalence checking using cuts," Pages: 455 - 458

SESSION: Analysis and simulation techniques

• Xiaolue Lai, Yayun Wan, Jaijeet Roychowdhury,"Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise," Pages: 459 - 464
• Fang Liu, Sule Ozev,"Hierarchical analysis of process variation for mixed-signal systems," Pages: 465 - 470
• Xuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou,"A novel wavelet method for noise analysis of nonlinear circuits," Pages: 471 - 476
• Mengmeng Ding, Glenn Wolfe, Ranga Vemuri,"An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels," Pages: 477 - 482

SESSION: Interconnect modeling and analysis and system level design methodology

• Yu Du, Wayne Dai,"Partial reluctance based circuit simulation is efficient and stable," Pages: 483 - 488
• Krishnan Srinivasan, Karam S. Chatha,"SAGA: synthesis technique for guaranteed throughput NoC architectures," Pages: 489 - 494
• Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane,"Automated throughput-driven synthesis of bus-based communication architectures," Pages: 495 - 498
• Jae-Gon Lee, Wooseung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung,"Simulation acceleration of transaction-level models for SoC with RTL sub-blocks," Pages: 499 - 502
• Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw,"Statistical modeling of cross-coupling effects in VLSI interconnects," Pages: 503 - 506
• Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong,"Compact and stable modeling of partial inductance and reluctance matrices," Pages: 507 - 510

SESSION: High-level synthesis

• Rami Beidas, Jianwen Zhu,"Scalable interprocedural register allocation for high level synthesis," Pages: 511 - 516
• Azadeh Davoodi, Ankur Srivastava,"Simultaneous floorplanning and resource binding: a probabilistic approach," Pages: 517 - 522
• Anup Hosangadi, Farzan Fallah, Ryan Kastner,"Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions," Pages: 523 - 528
• Rene Krenz, Elena Dubrova,"A fast algorithm for finding common multiple-vertex dominators in circuit graphs," Pages: 529 - 532

SESSION: Low power

• Abdulkadir U. Diril, Yuvraj S. Dhillon, Abhijit Chatterjee, Adit D. Singh,"Low-power domino circuits using NMOS pull-up on off-critical paths," Pages: 533 - 538
• Shengqi Yang, Wayne Wolf, Wenping Wang, N. Vijaykrishnan, Yuan Xie,"Low-leakage robust SRAM cell design for sub-100nm technologies," Pages: 539 - 544
• Ismail Kadayif, Mahmut Kandemir, Guilin Chen,"Studying interactions between prefetching and cache line turnoff," Pages: 545 - 548
• Wei Han, A. T. Erdogan, T. Arslan, M. Hasan,"The development of high performance FFT IP cores through hybrid low power algorithmic methodology," Pages: 549 - 552
• Newton Cheung, Sri Parameswaran, Jorg Henkel,"Battery-aware instruction generation for embedded processors," Pages: 553 - 556
• Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura,"A variation-aware low-power coding methodology for tightly coupled buses," Pages: 557 - 560

SESSION: Formal verification: theory and practice

• Dong Wang, Jeremy Levitt,"Automatic assume guarantee analysis for assertion-based formal verification," Pages: 561 - 566
• Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi,"TED+: a data structure for microprocessor verification," Pages: 567 - 572
• Rene Krenz, Elena Dubrova,"Improved Boolean function hashing based on multiple-vertex dominators," Pages: 573 - 578
• Rudiger Ebendt, Rolf Drechsler,"Lower bounds for dynamic BDD reordering," Pages: 579 - 582
• Xiushan Feng, Alan J. Hu, Jin Yang,"Partitioned model checking from software specifications," Pages: 583 - 587

SESSION: Special session

• Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe,"Are we ready for system-level synthesis?," Pages: 1 - 1

SESSION: Robust and low-power clock design

• Yongqiang Lu, C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu,"Register placement for low power clock network," Pages: 588 - 593
• Ganesh Venkataraman, C. N. Sze, Jiang Hu,"Skew scheduling and clock routing for improved tolerance to process variations," Pages: 594 - 599
• Vinil Varghese, Tom Chen, Peter Young,"Stability analysis of active clock deskewing systems using a control theoretic approach," Pages: 600 - 605
• Wai-Ching Douglas Lam, Cheng-Kok Koh,"Process variation robust clock tree routing," Pages: 606 - 611

SESSION: DSP

• Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Jerraya, Pascal Urard,"IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems," Pages: 612 - 618
• Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera,"A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing," Pages: 619 - 622
• Lingfeng Li, Satoshi Goto, Takeshi Ikenaga,"An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC," Pages: 623 - 626
• Yanjun Zhang, Hu he, Yihe Sun,"A new register file access architecture for software pipelining in VLIW processors," Pages: 627 - 630
• Minho Kim, Ingu Hwang, Soo-Ik Chae,"A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264," Pages: 631 - 634
• Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan,"Automatic synthesis and scheduling of multirate DSP algorithms," Pages: 635 - 638

SESSION: Low power and special purpose FPGAs

• Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay,"A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines," Pages: 639 - 644
• Yan Lin, Fei Li, Lei He,"Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction," Pages: 645 - 650
• Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia,"Exploiting temporal idleness to reduce leakage power in programmable architectures," Pages: 651 - 656
• Vijay Degalahal, Tim Tuan,"Methodology for high level estimation of FPGA power consumption," Pages: 657 - 660
• Suresh Srinivasan, A. Gayasen, N. Vijaykrishnan, T. Tuan,"Leakage control in FPGA routing fabric," Pages: 661 - 664

SESSION: RF circuit design and design methodology

• K. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian,"A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion," Pages: 665 - 670
• Min Chu, David J. Allstot,"An elitist distributed particle swarm algorithm for RF IC optimization," Pages: 671 - 674
• Min Chu, David J. Allstot,"Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization," Pages: 675 - 678
• Miao Li, Tad Kwasniewski, Shoujun Wang, Yuming Tao,"A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18ƒÊm CMOS technology," Pages: 679 - 682
• Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu,"A dynamic reconfigurable RF circuit architecture," Pages: 683 - 686
• Zhangwen Tang, Jie He, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min,"Prediction of LC-VCOs' tuning curves with period calculation technique," Pages: 687 - 690

SESSION: Design techniques in embedded and real-time system

• Zhihui Xiong, Jihua Chen, Sikun Li,"Hardware/software partitioning for platform-based design method," Pages: 691 - 696
• Ernesto Wandele, Lothar Thiele,"Abstracting functionality for modular performance analysis of hard real-time systems," Pages: 697 - 702
• Dongkun Shin, Jihong Kim,"Optimizing intra-task voltage scheduling using data flow analysis," Pages: 703 - 708
• John Conner, Yuan Xie, Mahmut Kandemir, Robert Dick, Greg Link,"FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection," Pages: 709 - 712
• G. Chen, M. Kandemir, M. J. Irwin, G. Memik,"Compiler-directed selective data protection against soft errors," Pages: 713 - 716

SESSION: Crosstalk noise avoidance and power/ground network optimization

• Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet M. Wang-Roveda,"A perturbation-aware noise convergence methodology for high frequency microprocessors," Pages: 717 - 722
• Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera,"Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion," Pages: 723 - 728
• Raid Ayoub, Alex Orailoglu,"A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses," Pages: 729 - 734
• Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan,"VLSI on-chip power/ground network optimization considering decap leakage currents," Pages: 735 - 738
• Jinjun Xiong, Lei He,"Probabilistic congestion model considering shielding for crosstalk reduction," Pages: 739 - 742

SESSION: Others in leading edge designs

• O. Ozturk, M. Kandemir, G. Chen, M. J. Irwin, M. Karakoy,"Customized on-chip memories for embedded chip multiprocessors," Pages: 743 - 748
• Rutuparna Ramesh Tamhankar, Srinivasan Murali, Giovanni De Micheli,"Performance driven reliable link design for networks on chips," Pages: 749 - 754
• Yuvraj Agarwal, Curt Schurgers, Rajesh Gupta,"Dynamic power management using on demand paging for networked embedded systems," Pages: 755 - 759
• Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi,"An FPGA implementation of low-density parity-check code decoder with multi-rate capability," Pages: 760 - 763
• Xiao Yong, Zhou Runde,"Single-track asynchronous pipeline controller design," Pages: 764 - 768
• M. Kandemir, G. Chen, F. Li, I. Demirkiran,"Using data replication to reduce communication energy on chip multiprocessors," Pages: 769 - 772

SESSION: Synthesis for FPGAs

• Cristinel Ababei, Hushrav Mogal, Kia Bazargan,"Three-dimensional place and route for FPGAs," Pages: 773 - 778
• Wai-Kei Mak,"Modern FPGA constrained placement," Pages: 779 - 784
• Chang Woo Kang, Massoud Pedram,"Clustering techniques for coarse-grained, antifuse FPGAs," Pages: 785 - 790
• Vivek Garg, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti,"A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs," Pages: 791 - 794
• Somsubhra Mondal, Seda O?renci Memik,"Resource sharing in pipelined CDFG synthesis," Pages: 795 - 798

SESSION: Analog circuit design

• Hong Zhang, Guican Chen, Ning Li,"A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillator," Pages: 799 - 802
• Guoqiang Hang,"Adiabatic CMOS gate and adiabatic circuit design for low-power applications," Pages: 803 - 808
• Osamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta,"An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system," Pages: 809 - 814
• Chen Hai, Wu Xiaobo,"A class D audio power amplifier with high-efficiency and low-distortion," Pages: 815 - 818
• Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang,"Substrate noise modeling in early floorplanning of MS-SOCs," Pages: 819 - 823

SESSION: Low power design for embedded and real-time systems

• Shu Xiao, Edmund M-K. Lai,"Instruction scheduling of VLIW architectures for balanced power consumption," Pages: 824 - 829
• Shaoxiong Hua, Gang Qu,"Power minimization techniques on distributed real-time systems by global and local slack management," Pages: 830 - 835
• Jaewon Seo, Nikil D. Dutt,"A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors," Pages: 836 - 841
• Van R. Culver, Sunil P. Khatri,"A dynamic voltage scaling algorithm for energy reduction in hard real-time systems," Pages: 842 - 845
• Jianli Zhuo, Chaitali Chakrabarti,"An efficient dynamic task scheduling algorithm for battery powered DVS systems," Pages: 846 - 849

SESSION: Synthesis for low power

• Deming Chen, Jason Cong, Junjuan Xu,"Optimal module and voltage assignment for low-power," Pages: 850 - 855
• Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng,"Bitwidth-aware scheduling and binding in high-level synthesis," Pages: 856 - 861
• Tsuang-Wei Chang, Ting-Ting Hwang, Sheng-Yu Hsu,"Functionality directed clustering for low power MTCMOS design," Pages: 862 - 867
• Azadeh Davoodi, Ankur Srivastava,"Wake-up protocols for controlling current surges in MTCMOS-based technology," Pages: 868 - 871
• Hsueh-Chih Yang, Lan-Rong Dung,"On multiple-voltage high-level synthesis using algorithmic transformations," Pages: 872 - 876

SESSION: New circuit and methodology

• Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim,"An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin," Pages: 877 - 882
• Haikun Zhu, Chung-Kuan Cheng, Ronald Graham,"Constructing zero-deficiency parallel prefix adder of minimum depth," Pages: 883 - 888
• Zhangwen Tang, Jie He, Hongyan Jian, Hao Min,"An accurate 1.08-GHz CMOS LC voltage-controlled oscillator," Pages: 889 - 892
• Anru Wang, Wayne Dai,"Area-IO DRAM/logic integration with system-in-a-package (SiP)," Pages: 893 - 896
• Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li,"Design of an efficient memory subsystem for network processor," Pages: 897 - 900
• Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh Kumar Pilakkat,"Design of clocked circuits using UML," Pages: 901 - 904

SESSION: FPGA circuits and architectures

• Vivek Garg, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti,"A function generator-based reconfigurable system," Pages: 905 - 909
• Hongbing Fan, Yu-Liang Wu,"Crossbar based design schemes for switch boxes and programmable interconnection networks," Pages: 910 - 915
• Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay,"A domain specific reconfigurable Viterbi fabric for system-on-chip applications," Pages: 916 - 919
• Chu Chao, Zhang Qin, Xie Yingke, Han Chengde,"Design of a high performance FFT processor based on FPGA," Pages: 920 - 923
• G. Chen, F. Li, M. Kandemir, I. Demirkiran,"Increasing FPGA resilience against soft errors using task duplication," Pages: 924 - 927
• Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee,"Automatic extraction of function bodies from software binaries," Pages: 928 - 931

SESSION: (Special session) EDA market in China

• David Chen, Nancy Wu, Wayne Dai, Jun Tan, Weiping Liu, Hao Min, Jian-yue Pan,"Panel III: EDA market in China," Pages: 1 - 1

SESSION: Poster session I

• Chen Xi, Lu JianHua, Zhou ZuCheng, Shang YaoHui,"Modeling SystemC design in UML and automatic code generation," Pages: 932 - 935
• M. AbdElSalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai,"Enabling RTOS simulation modeling in a system level design language," Pages: 936 - 939
• Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti,"A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems," Pages: 940 - 943
• Lukai Cai, Andreas Gerstlauer, Daniel Gajski,"Multi-metric and multi-entity characterization of applications for early system design exploration," Pages: 944 - 947
• Yongxin Zhu, Weng-Fai Wong, ?tefan Andrei,"An integrated performance and power model for superscalar processor designs," Pages: 948 - 951
• Zhe Ma, Francky Catthoor, Johan Vounckx,"Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms," Pages: 952 - 955
• Praveen Kalla, Xiaobo Sharon Hu, Jorg Henkel,"A flexible framework for communication evaluation in SoC design," Pages: 956 - 959
• Zhonghai Lu, Axel Jantsch, Ingo Sander,"Feasibility analysis of messages for on-chip networks using wormhole routing," Pages: 960 - 964
• Junyu Peng, Samar Abdi, Daniel Gajski,"A clustering technique to optimize hardware/software synchronization," Pages: 965 - 968
• Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed A. Jerraya,"Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration," Pages: 969 - 972
• Chunhui Zhang, Fadi Kurdahi,"On combining iteration space tiling with data space tiling for scratch-pad memory systems," Pages: 973 - 976
• Zoran Salcic, Dong Hui, Partha Roop, Morteza Biglari-Abhari,"REMIC: design of a reactive embedded microprocessor core," Pages: 977 - 981
• Thilo Streichert, Christian Haubelt, Jurgen Teich,"Online hardware/software partitioning in networked embedded systems," Pages: 982 - 985
• Lisane Brisolara, Leandro Becker, Luigi Carro, Flavio Wagner, Carlos E. Pereira, Ricardo Reis,"Comparing high-level modeling approaches for embedded system design," Pages: 986 - 989
• Hai Zhou,"Deriving a new efficient algorithm for min-period retiming," Pages: 990 - 993
• Kuo-Hua Wang, Jia-Hung Chen,"K-disjointness paradigm with application to symmetry detection for incompletely specified functions," Pages: 994 - 997
• Petra Farm, Elena Dubrova, Andreas Kuehlmann,"Logic optimization using rule-based randomized search," Pages: 998 - 1001
• Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski,"Fast synthesis of exact minimal reversible circuits using group theory," Pages: 1002 - 1005
• Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone,"Design and design automation of rectification logic for engineering change," Pages: 1006 - 1009
• Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh,"Power minimization for dynamic PLAs," Pages: 1010 - 1013
• Shuo Zhou, Bo Yao, Jian-Hua Liu, Chung-Kuan Cheng,"Integrated algorithmic logical and physical design of integer multiplier," Pages: 1014 - 1017
• R. Ruiz-Sautua, M. C. Molina, J. M. Mendias, R. Hermida,"Arrival time aware scheduling to minimize clock cycle length," Pages: 1018 - 1021
• W. B. Toms, D. A. Edwards,"Efficient synthesis of speed-independent combinational logic circuits," Pages: 1022 - 1026
• Peter Suaris, Dongsheng Wang, Nan-Chi Chou,"A practical cut-based physical retiming algorithm for field programmable gate arrays," Pages: 1027 - 1030
• Dennis Wu, Jianwen Zhu,"BDD-based two variable sharing extraction," Pages: 1031 - 1034

SESSION: Poster session II

• Ed Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Tony Ma,"Supporting sequential assumptions in hybrid verification," Pages: 1035 - 1038
• Tun Li, Dan Zhu, Lei Liang, Yang Guo, SiKun Li,"Automatic functional test program generation for microprocessor verification," Pages: 1039 - 1042
• Georgios Logothetis,"Forward symbolic model checking for real time systems," Pages: 1043 - 1046
• Yinlei Yu, Sharad Malik,"Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice," Pages: 1047 - 1051
• Hao Shen, Yuzhuo Fu,"Priority directed test generation for functional verification using neural networks," Pages: 1052 - 1055
• Miroslav N. Velev,"Comparison of schemes for encoding unobservability in translation to SAT," Pages: 1056 - 1059
• Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song,"Implication of assertion graphs in GSTE," Pages: 1060 - 1063
• Qing XU, Carl Tropper,"XTW, a parallel and distributed logic simulator," Pages: 1064 - 1069
• Rong Jiang, Charlie Chung-Ping Chen,"Comprehensive frequency dependent interconnect extraction and evaluation methodology," Pages: 1070 - 1073
• Takashi Sato, Junji Ichimiya, Nobuto Ono, Kotaro Hachiya, Masanori Hashimoto,"On-chip thermal gradient analysis and temperature flattening for SoC design," Pages: 1074 - 1077
• Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera,"Return path selection for loop RL extraction," Pages: 1078 - 1081
• Natalie Nakhla, Ram Achar, Michel Nakhla, Anestis Dounavis,"Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects," Pages: 1082 - 1085
• Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li,"Vector extraction for average total power estimation," Pages: 1086 - 1089
• Yici Cai, Zhu Pan, Shelton X-D Tan, Xianlong Hong, Wenting Hou, Lifeng Wu,"Relaxed hierarchical power/ground grid analysis," Pages: 1090 - 1093
• Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan,"Sleep transistor sizing using timing criticality and temporal currents," Pages: 1094 - 1097
• Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera,"Timing analysis considering temporal supply voltage fluctuation," Pages: 1098 - 1101
• G Peter Fang, David C Yeh, David Zweidinger, Lawrence A Arledge, Vinod Gupta,"Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity," Pages: 1102 - 1106
• Chiu-wing Sham, Evangeline F. Y. Young,"Congestion prediction in floorplanning," Pages: 1107 - 1110
• Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong,"CMP aware shuttle mask floorplanning," Pages: 1111 - 1114
• Renshen Wang, Sheqin Dong, Xianlong Hong,"An improved P-admissible floorplan representation based on Corner Block List," Pages: 1115 - 1118
• Jason Cong, Michail Romesis, Joseph R. Shinnerl,"Fast floorplanning by look-ahead enabled recursive bipartitioning," Pages: 1119 - 1122
• Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu,"LFF algorithm for heterogeneous FPGA floorplanning," Pages: 1123 - 1126
• Mongkol Ekpanyapong, Michael Healy, Sung Kyu Lim,"Placement for configurable dataflow architecture," Pages: 1127 - 1130
• Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim,"Wire congestion and thermal aware 3D global placement," Pages: 1131 - 1134
• Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang,"Placement with symmetry constraints for analog layout design using TCG-S," Pages: 1135 - 1137

SESSION: Poster session III

• Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal,"An LP-based methodology for improved timing-driven placement," Pages: 1139 - 1143
• Chuck J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet C. YILDIZ,"Placement stability metrics," Pages: 1144 - 1147
• Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong,"Redundant-via enhanced maze routing for yield improvement," Pages: 1148 - 1151
• Jia Wang, Hai Zhou,"Interconnect estimation without packing via ACG floorplans," Pages: 1152 - 1155
• Di Wu, Jiang Hu, Min Zhao, Rabi Mahapatra,"Timing driven track routing considering coupling capacitance," Pages: 1156 - 1159
• Tai-Chen Chen, Yao-Wen Chang,"Multilevel full-chip gridless routing considering optical proximity correction," Pages: 1160 - 1163
• Ruibing Lu, Aiqun Cao, Cheng-Kok Koh,"Improving the scalability of SAMBA bus architecture," Pages: 1164 - 1167
• Jeng-Liang Tsai, Charlie Chung-Ping Chen,"Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling," Pages: 1168 - 1171
• Ho Fai Ko, Qiang Xu, Nicola Nicolici,"Register-transfer level functional scan for hierarchical designs," Pages: 1172 - 1175
• Yu Huang, Wu-Tung Cheng, Greg Crowell,"Using fault model relaxation to diagnose real scan chain defects," Pages: 1176 - 1179
• Baosheng Wang, Josh Yang, Yuejian Wu, Andre Ivanov,"A retention-aware test power model for embedded SRAM," Pages: 1180 - 1183
• Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang,"On-chip accumulated jitter measurement for phase-locked loops," Pages: 1184 - 1187
• Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang,"SoC test scheduling using the B-tree based floorplanning technique," Pages: 1188 - 1191
• Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu,"Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands," Pages: 1192 - 1195
• Ying Chen, Dennis Abts, David J. Lilja,"Efficiently generating test vectors with state pruning," Pages: 1196 - 1199
• E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan,"Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs," Pages: 1200 - 1203
• Dong Feng, Bingxue Shi,"Comprehensive analysis and optimization of CMOS LNA noise performance," Pages: 1204 - 1207
• Jung-Hyun Cho, Suk-Byung Chai, Chung-Gi Song, Kyung-Won Min, Shiho Kim,"An analog front-end IP for 13.56MHz RFID interrogators," Pages: 1208 - 1211
• A. Zahabi, O. Shoaei, Y. Koolivand, P. Jabehdar-maralani,"A two-stage genetic algorithm method for optimization the ƒ°ƒ¢ modulators," Pages: 1212 - 1215
• Gong Qian, Yuan Guo-shun,"A novel differential VCO circuit design for USB Hub," Pages: 1216 - 1219
• M. S. Bhat, H. S. Jamadagni,"Static power minimization in current-mode circuits," Pages: 1220 - 1223
Pages: 1224 - 1227
• Yongjian Tang, Lenian He, Xiaolang Yan,"A novel data processing circuit in high-speed serial communication," Pages: 1228 - 1231
• Ziqiang Wang, Baoyong Chi, Min Lin, Shuguang Han, Lu Liu, Jinke Yao, Zhihua Wang,"A monolithic CMOS L band DAB receiver," Pages: 1232 - 1235
• Yonggang Tao, Yongsheng Xu, Wei Jin, Hui Yu, Zongsheng Lai,"A bipolar IF amplifier/RSSI for ASK receiver," Pages: 1236 - 1239

SESSION: Poster session IV

• Rajarshi Mukherjee, Seda Ogrenci Memik,"Evaluation of dual VDD fabrics for low power FPGAs," Pages: 1240 - 1243
• Jae-Jin Lee, Gi-Yong Song,"Design of an application-specific PLD architecture," Pages: 1244 - 1247
• Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita,"Event-oriented computing with reconfigurable platform," Pages: 1248 - 1251
• Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto,"Reconfigurable adaptive FEC system with interleaving," Pages: 1252 - 1255
• Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioannis Nousias, Iain Lindsay,"An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks," Pages: 1256 - 1259
• Xin Jia, Ranga Vemuri,"Using GALS architecture to reduce the impact of long wire delay on FPGA performance," Pages: 1260 - 1263
• Tiejun Li, Sikun Li, Chengdong Shen,"A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding," Pages: 1264 - 1267
• Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong,"A fast digit-serial systolic multiplier for finite field GF(2m)," Pages: 1268 - 1271
• Zhu Xiangbin, Tu ShiLiang,"Adaptive fuzzy control scheduling of window-constrained real-time systems," Pages: 1272 - 1275
• Bo Shen, Junhua Tian, Zheng Li, Jianing Su, Qianling Zhang,"A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder," Pages: 1276 - 1279
• Lin Xie, Peiliang Qiu, Qinru Qiu,"Partitioned bus coding for energy reduction," Pages: 1280 - 1283
• Yanju Han, Chao Xu, Yizhen Zhang,"An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000," Pages: 1284 - 1287
• Yi-Ran Sun, Svante Signell,"A generalized quadrature bandpass sampling in radio receivers," Pages: 1288 - 1291
• Xin Lu, Yuzhuo Fu,"Reducing leakage power in instruction cache using WDC for embedded processors," Pages: 1292 - 1295
• Qiang Wu, Jinian Bian, Hongxi Xue,"System-level architectural exploration using allocation-on-demand technique," Pages: 1296 - 1298
• P. Torkzadeh, A. Tajalli, M. Atarodi,"A fractional delay-locked loop for on chip clock generation applications," Pages: 1300 - 1309
• Jaehwan John Lee, Vincent John Mooney, III,"A novel O(n) parallel banker's algorithm for System-on-a-Chip," Pages: 1304 - 1308
• Zhihui Xiong, Sikun Li, Jihua Chen,"Hardware/software co-design using hierarchical platform-based design method," Pages: 1309 - 1312
• Yan Zhang,"Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip," Pages: 1313 - 1316
• Sri Hari Krishna N, Seung Woo Son, Mahmut Kandemir, Feihui Li,"Using loop invariants to fight soft errors in data caches," Pages: 1317 - 1320