| Title | Stochastic Thermal Simulation Considering Spatial Correlated Within-Die Process Variations |
| Author | *Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee (National Chiao Tung University, Taiwan) |
| Page | pp. 31 - 36 |
| Keyword | Statistical IC thermal simulator, Karhunen-Loeve expansion, Leakage power, stochastic Galerkin method |
| Abstract | In this work, a statistical thermal simulator including
the effect of spatial correlation under within-die process variations
is developed. This method utilizes the Karhunen-Loeve
(KL) expansion to model the physical parameters, and applies the
Polynomial Chaoses (PCs) and the stochastic Galerkin method to
tackle the stochastic heat transfer equations. The experimental
results not only demonstrate the accuracy and efficiency of the
proposed method, but also point out that the stochastic thermal
analysis is essential to provide a robust estimation of temperature
distribution for the thermal-aware design flow. |
| Title | A Control Theory Approach for Thermal Balancing of MPSoC |
| Author | *Francesco Zanini, David Atienza, Giovanni De Micheli (Ecole Polytechnique Federale de Lausanne, Switzerland) |
| Page | pp. 37 - 42 |
| Keyword | thermal balancing, MPSoC, control theory, linear quadratic regulator |
| Abstract | Thermal balancing and reducing hot-spots are two
important challenges facing the MPSoC designers. In this work,
we model the thermal behavior of an MPSoC as a control theory
problem, which enables the design of an optimum frequency
controller without depending on the thermal profile of the chip.
The optimization performed by the controller is targeted to
achieve thermal balancing on the MPSoC thermal profile to avoid
hotspots and improve its reliability. The proposed system is able
to perform an on-line minimization of chip thermal gradients
based on both scheduler requirements and the chip thermal profile.
We compare this with state of the art thermal management
approaches, our comparison shows that the proposed system offers
a better both thermal profile (temperature differences higher
than 4±C have been reduced from 27.9% to 0.45%) and performance
(up to 32% task waiting time reduction). |
| Title | Thermal Optimization in Multi-Granularity Multi-Core Floorplanning |
| Author | *Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim (Georgia Institute of Technology, United States) |
| Page | pp. 43 - 48 |
| Keyword | multicore, thermal, floorplanning |
| Abstract | Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of these factors at an early stage. Toward this goal, this work presents the first adaptive multi-granularity multi-core microarchitecture-level floorplanner that simultaneously optimizes temperature and performance, and considers memory bus length. We include simultaneous optimization at both the module-level and the core/cache-bank level. Related experiments show that our methodology is effective for optimizing multi-core architectures. |
| Title | Temperature-Aware Dynamic Frequency and Voltage Scaling for Reliability and Yield Enhancement |
| Author | *Yu-Wei Yang, Katherine Shu-Min Li (Department of Computer Science and Engineering, National Sun Yat-Sen University, Taiwan) |
| Page | pp. 49 - 54 |
| Keyword | DVFS, DVS, oscillation ring, on-chip thermal sensors, on-chip DVFS monitor |
| Abstract | A novel oscillation-based on-chip thermal sensing
architecture for dynamically adjusting supply voltage and clock
frequency in System-on-Chip (SoC) is proposed. It is shown
that the oscillation frequency of a ring oscillator reduces
linearly as the temperature rises, and thus provides a good
on-chip temperature sensing mechanism. An efficient Dynamic
Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed
to dynamically adjust supply voltage according to the
oscillation frequencies of the ring oscillators distributed in SoC
so that thermal sensing can be carried at all potential hot spots.
An on-chip Dynamic Voltage Scaling or Dynamic Voltage and
Frequency Scaling (DVS or DVFS) monitor selects the supply
voltage level and clock frequency according to the outputs of all
thermal sensors. Experimental results on SoC benchmark
circuits show the effectiveness of the algorithm that a 10%
reduction in supply voltage alone can achieve about 20% power
reduction (DVS scheme), and nearly 50% reduction in power is
achievable if the clock frequency is also scaled down (DVFS
scheme). The chip temperature is reduced accordingly. |
| Slides |
| Title | A Multiple Supply Voltage Based Power Reduction Method in 3-D ICs Considering Process Variations and Thermal Effects |
| Author | Shih-An Yu, *Pei-Yu Huang, Yu-Min Lee (National Chiao Tung University, Taiwan) |
| Page | pp. 55 - 60 |
| Keyword | Power Optimization, 3D ICs, Thermal analysis, Multiple Supply Voltage |
| Abstract | In this paper, a grid-based multiple supply voltage
(MSV) assignment method is presented to statistically minimize
the total power consumption of 3-D IC. This method consists of
a statistical electro-thermal simulator to get the mean and variance
of on-chip, a thermal-aware statistical static timing analysis
(SSTA) to take into account the thermal effect on circuit timing,
the statistical power delay sensitivity–slack product to be the optimization
criterion, and an incremental update of statistical timing
to save the runtime. The experimental results demonstrate
the effectiveness of the developed methodology and indicate that
the consideration of the thermal effect in the circuit simulation is
imperative. |