| Title | Statistical Modeling and Analysis of Chip-Level Leakage Power by Spectral Stochastic Method |
| Author | Ruijing Shen, Ning Mi, *Sheldon Tan (University of California at Riverside, United States), Yici Cai, Xianlong Hong (Tsinghua University, China) |
| Page | pp. 161 - 166 |
| Keyword | Leakage analysis, orthogonal polynomials, variational analysis |
| Abstract | In this paper, we present a novel statistical full-chip leakage
power analysis method. The new method can provide a general
framework to derive the full-chip leakage current or power in a
closed form in terms of the variational parameters, such as the
channel length, the gate oxide thickness, etc. It can accommodate
various spatial correlations. The new method employs the
orthogonal polynomials to represent the variational gate leakages
in a closed form first, which is generated by a fast
multi-dimensional Gaussian quadrature method. The total leakage
currents then are computed by simply summing up the resulting
orthogonal polynomials (their coefficients). Unlike many existing
approaches, no grid-based partitioning and approximation are
required. Instead, the spatial correlations are naturally handled
by orthogonal decompositions. The proposed method is very
efficient and it becomes linear when there exist strong spatial
correlations. Experimental results show that the proposed method
is about 10X faster than the recently proposed
method~\cite{Chang:DAC'05} with constant better accuracy. |
| Title | On the Futility of Statistical Power Optimization |
| Author | Jason Cong, Puneet Gupta, *John Lee (University of California, Los Angeles, United States) |
| Page | pp. 167 - 172 |
| Keyword | gate sizing, optimization, statistical power |
| Abstract | In response to the increasing variations in integrated-circuit
manufacturing, the current trend is to create designs that take
these variations into account statistically. In this paper we try
to quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions
about the delay model. We develop a framework for deriving a
theoretical upper-bound on the suboptimality that is incurred
by using the deterministic optimum as an approximation for the statistical optimum. On average, the bound is 2.4% for a suite of
benchmark circuits in a 45nm technology. We further give an
intuitive explanation and show, by using solution rank orders,
that the practical suboptimality gap is much lower. There-
fore, the need for statistical power modeling for the purpose
of optimization is questionable. |
| Slides |
| Title | Timing Driven Power Gating in High-Level Synthesis |
| Author | Shih-Hsu Huang, *Chun-Hua Cheng (Chung Yuan Christian University, Taiwan) |
| Page | pp. 173 - 178 |
| Keyword | Clock Skew Scheduling, High-Level Synthesis, Low Power Design, Resource Binding, Standby Leakage Minimization |
| Abstract | The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work to draw up the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show: compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead. |
| Slides |
| Title | Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors |
| Author | Pingqiang Zhou, Karthikk Sridharan, *Sachin S. Sapatnekar (ECE Dept, University of Minnesota, United States) |
| Page | pp. 179 - 184 |
| Keyword | 3D circuit, power grid, MIM decap, leakage power, congestion |
| Abstract | In three-dimensional (3D) chips, the amount of supply current per
package pin is significantly more than in two-dimensional (2D)
designs. Therefore, the power supply noise problem, already a major
issue in 2D, is even more severe in 3D. CMOS decoupling capacitors
(decaps) have been used effectively for controlling power grid noise
in the past, but with technology scaling, they have grown
increasingly leaky. As an alternative, metal-insulator-metal (MIM)
decaps, with high capacitance densities and low leakage current
densities, have been proposed. In this paper, we explore the
tradeoffs between using MIM decaps and traditional CMOS decaps, and
propose a congestion-aware 3D power supply network optimization
algorithm to optimize this tradeoff. The algorithm applies a
sequence-of-linear-programs based method to find the optimum
tradeoff between MIM and CMOS decaps. Experimental results show that
power grid noise can be more effectively optimized after the
introduction of MIM decaps, with lower leakage power and little
increase in the routing congestion, as compared to a solution using
CMOS decaps only. |
| Slides |
| Title | Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis |
| Author | *Yiyu Shi, Wei Yao (Electrical Engineering Dept., University of California, Los Angeles, United States), Jinjun Xiong (IBM Thomas J. Watson Research Center, United States), Lei He (Electrical Engineering Dept., University of California, Los Angeles, United States) |
| Page | pp. 185 - 190 |
| Keyword | random walk, power grid, simulation, incremental analysis |
| Abstract | Power distribution networks (PDNs) are designed and analyzed iteratively. Randomwalk is among themost efficient methods for PDN analysis. We develop in this paper an incremental and on-demand random walk to reduce iterative analysis time. During each iteration, we map the design changes as positive or negative random walks for observed nodes. To update PDN analysis result, we only need to apply these extra positive or negative walks, instead of doing all walks from scratch. We show that different execution orders for these walks do not affect accuracy but do affect the runtime because of the cancellation between positive and negative walks. Considering this cancellation effect, we optimize the walk order by solving a min-energy electromagnetic particles placement problem and, as a result, further reduce the runtime to about 8× compared to the worst order. Experiments show that, compared to random walk from scratch, our algorithm has similar accuracy but reduces the iterative analysis time by up to 18× for on-chip PDN sizing, and by up to 13× for package ball assignment with substrate routing. In addition, our incremental random walk has a linear time complexity with respect to the number of observed nodes and is more suitable for on-demand analysis, compared to random walk from scratch and its big warm-up cost. |