| Title | Signal Skew Aware Floorplanning and Bumper Signal Assignment Technique for Flip-Chip |
| Author | *Cheng-Yu Wang, Wai-Kei Mak (Department of Computer Science, National Tsing Hua University, Taiwan) |
| Page | pp. 341 - 346 |
| Keyword | Flip-chip, floorplanning, Bumper, pad, Assignment |
| Abstract | Flip-chip is a solution for designs requiring more I/O pins and higher speed. However, the higher speed demand also brings the issue of signal skew. In this paper, we propose a new 3-stage design layout methodology for flip-chip considering signal skew. Firstly, we produce an initial bumper signal assignment, and then solve the flip-chip floorplanning problem using a partitioningbased technique to spread the modules across the flip-chip as the distribution of its bumpers. With an anchoring and relocation strategy, we can effectively place I/O buffers at desirable locations. Finally, we further reduce signal skew and monotonic routing density by refining the bumper signal assignment. Experimental results show that signal skew of traditional floorplanners range from 4% to 280% higher than ours. And the total wirelength of other floorplanners is as much as 100% higher than ours. Moreover, our signal refinement method can further decrease monotonic routing density by up to 8% and signal skew by up to 11% |
| Title | A Novel Thermal Optimization Flow Using Incremental Floorplanning for 3D ICs |
| Author | Xin Li, *Yuchun Ma, Xianlong Hong (Tsinghua University, China) |
| Page | pp. 347 - 352 |
| Keyword | 3D ICs, incremental floorplanning, thermal |
| Abstract | Thermal issue is a critical challenge in 3D IC design. To eliminate hotspots, physical layouts are always adjusted by shifting or duplicating hot blocks. However, these modifications may degrade the packing area as well as interconnect distribution greatly. In this paper, we propose some novel thermal-aware incremental changes to optimize these multiple objectives including thermal issue in 3D ICs. Furthermore, to avoid random incremental modification, which may be inefficient and need long runtime to converge, here potential gain is modeled for each candidate incremental change. Based on the potential gain, a novel thermal optimization flow to intelligently choose the best incremental operation is presented. We distinguish the thermal-aware incremental changes in three different categories: migrating computation, growing unit and moving hotspot. Mixed integer linear programming (MILP) models are devised according to these different incremental changes. Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks. Still, experimental results also show that the thermal optimization flow can reduce max on-chip temperature by 14% compared to an existing 3D floorplan tool CBA, and achieve better area and total wirelength improvement than individual operations do. |
| Title | Analog Placement with Common Centroid and 1-D Symmetry Constraints |
| Author | *Linfu Xiao, Evangeline Young (The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 353 - 360 |
| Keyword | analog placement, common centroid, symmetry |
| Abstract | In this paper, we will present a placement method for analog ircuits. We consider both common centroid and 1-D symmetry constraints, which are the two most common types of placement requirements in analog designs. The approach is based on a symmetric feasible condition on the sequence pair representation that can cover completely the set of all placements satisfying the common centroid and 1-D symmetry constraints. This condition is essential for a good searching process to solve the problem effectively. Symmetric placement is an important step to achieve matchings of other electrical properties like delay and temperature variation. We have compared our results with those presented in the most updated previous works. Significant improvements can be obtained by our approach in both common centroid and 1-D symmetry placements, and we are the first who can handle both constraints simultaneously. |
| Title | A Multilevel Analytical Placement for 3D ICs |
| Author | Jason Cong, *Guojie Luo (University of California, Los Angeles, United States) |
| Page | pp. 361 - 366 |
| Keyword | 3D IC, analytical placement, through-silicon via |
| Abstract | Abstract - In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method [1], we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers. |
| Slides | |
| Title | Exploring Adjacency in Floorplanning |
| Author | Jia Wang, *Hai Zhou (Northwestern University, United States) |
| Page | pp. 367 - 372 |
| Keyword | floorplanning, adjacency graph |
| Abstract | This paper describes a new floorplanning approach called Constrained Adjacency Graph (CAG) that helps exploring adjacency in floorplans. CAG extends the previous adjacency graph approaches by adding explicit adjacency constraints to the graph edges. After sufficient and necessary conditions of CAG are developed based on dissected floorplans, CAG is extended to handle general floorplans in order to improve area without changing the adjacency relations dramatically. These characteristics are currently utilized in a randomized greedy improvement heuristic for wire length optimization. The results show that better floorplans are found with much less running time for problems with 100 to 300 modules in comparison to a simulated annealing floorplanner based on sequence pairs. |