| Title | System-Level Exploration Tool for Energy-Aware Memory Management in the Design of Multidimensional Signal Processing Systems |
| Author | *Florin Balasa (Southern Utah University, United States), Ilie I. Luican (University of Illinois at Chicago, United States), Hongwei Zhu (ARM, Inc., United States), Doru V. Nasui (American International Radio, Inc., United States) |
| Page | pp. 443 - 448 |
| Keyword | multidimensional signal processing, memory management, memory allocation, signal-to-memory assignment, dynamic energy consumption |
| Abstract | Many signal processing systems, particularly in the multimedia and telecom domains, are synthesized to execute data-dominated applications. Their behavior is described in a high-level programming language, where the code is typically organized in sequences of loop nests and the main data structures are multidimensional arrays. Since data transfer and storage have a significant impact on both the system performance and the major cost parameters -- power consumption and chip area, the designer must spend a significant effort during the system development process on the exploration of the memory subsystem in order to achieve a cost-optimized design. This paper presents a software tool for system-level exploration, where several memory management tasks are addressed in a common theoretical framework. The tool can compute the minimum storage requirement of a given application and can produce the graph of storage variation during the code execution; it offers memory allocation and signal assignment solutions both for flat and hierarchical organizations and optimizes the dynamic energy consumption in the memory subsystem. |
| Title | Systematic Architecture Exploration based on Optimistic Cycle Estimation for Low Energy Embedded Processors |
| Author | *Ittetsu Taniguchi (Osaka University, Japan), Murali Jayapala (IMEC vzw., Belgium), Praveen Raghavan, Francky Catthoor (IMEC vzw./K.U.Leuven, Belgium), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 449 - 454 |
| Keyword | architecture exploration, address generation unit (AGU), reconfigurable architecture |
| Abstract | Systematic architecture exploration from vast solution space is a complex problem in embedded system design. It is very difficult to explore a best architecture fast and accurately because accurate evaluation usually consumes significant amount of time for point in the solution space. In this paper, we propose fast and systematic architecture exploration method for address generation unit (AGU) based on a coarse grained reconfigurable architecture model. First we prove that a set of Pareto solutions of cycle vs energy becomes a subset of Pareto solutions of cycle vs area under some practical assumptions. In addition we propose ``Optimistic cycle (OC)'' metric to find out promising solutions from vast solution space. Based on this metric we also propose a fast architecture exploration algorithm which only applies mapping to promising architectures. Using the proposed systematic architecture exploration method, we show that we can obtain almost the same trade-off points as the exhaustive search method and also that our method is about 164 times faster than exhaustive search. |
| Slides | |
| Title | A Framework for Estimating NBTI Degradation of Microarchitectural Components |
| Author | *Michael DeBole, Ramakrishnan Krishnan (The Pennsylvania State University, United States), Varsha Balakrishnan, Wenping Wang (Arizona State University, United States), Hong Luo, Yu Wang (Tsinghua University, China), Yuan Xie (The Pennsylvania State University, United States), Yu Cao (Arizona State University, United States), N. Vijaykrishnan (The Pennsylvania State University, United States) |
| Page | pp. 455 - 460 |
| Keyword | NBTI, Reliability, CAD, Computer Architecture |
| Abstract | Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from NBTI is of particular concern in deep submicron technology generations. To facilitate architectural level aging analysis, a tool capable of evaluating NBTI vulnerabilities early in the design cycle has been developed. The tool includes workload-based temperature and performance degradation analysis across a variety of technologies and operating conditions, revealing a complex interplay between factors influencing NBTI timing degradation. |