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The 14th Asia and South Pacific Design Automation Conference

Session 7A  Compilation Techniques for Embedded Systems
Time: 10:15 - 12:20 Thursday, January 22, 2009
Location: Room 411+412
Chairs: Hiroyuki Tomiyama (Nagoya University, Japan), Maziar Goudarzi (Kyushu University, Japan)

7A-1 (Time: 10:15 - 10:40)
TitleThermal-aware Post Compilation for VLIW Architectures
Author*Wen-Wen Hsieh, TingTing Hwang (Department of Computer Science, National Tsing Hua University, Taiwan)
Pagepp. 606 - 611
Keywordthermal management, Post Compilation, VLIW architecture
AbstractDevelopment of a thermal management method to reduce hotspots and to balance the temperature distribution has become an important issue. In this paper, we propose a static thermal management technique at compiler level. The target machine is a VLIW architecture where the compiler is required to schedule instructions to achieve instruction level parallelism (ILP). Two technique are proposed. The first one is register binding to balance the temperature of the register file by taking both spatial and temporal thermal information into consideration. The second one is forwarding methods including forwarding-aware architecture and instruction scheduling to reduce the access count of register file. The experimental results show that by combining the two techniques, the peak temperature reduction can reach 7.89 (oC) in the best case and 7.22 (oC) in average with only 0.9% performance penalty in average.
Slides

7A-2 (Time: 10:40 - 11:05)
TitleA Software Solution for Dynamic Stack Management on Scratch Pad Memory
AuthorArun Kannan, *Aviral Shrivastava, Amit Pabalkar, Jong-eun Lee (Arizona State University, United States)
Pagepp. 612 - 617
Keywordscratch pad, cache, stack, power, compiler
AbstractWe propose a dynamic scratch pad memory (SPM) management scheme for program stack data for processor power reduction. As opposed to previous efforts, our solution does not mandate any hardware changes, does not need profile information, and SPM size at compile-time, and seamlessly integrates support for recursive functions. Our technique manages stack frames on SPM using a scratch pad memory manager (SPMM), integrated into the application binary by the compiler. Our experiments on benchmarks from MiBench [18] show average energy savings of 37% along with a performance improvement of 18%.

7A-3 (Time: 11:05 - 11:30)
TitleCompiler-Managed Register File Protection for Energy-Efficient Soft Error Reduction
AuthorJongeun Lee, *Aviral Shrivastava (Arizona State University, United States)
Pagepp. 618 - 623
Keywordsoft error, register file, power-efficient, compiler, register allocation
AbstractFor embedded systems where neither energy nor reliability can be easily sacrificed, we present an energy efficient soft error protection scheme for register files (RF). Unlike previous approaches, our method explicitly optimizes for energy efficiency and exploits the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme is more energy efficient than hardware schemes, this work formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 24%.

7A-4 (Time: 11:30 - 11:55)
TitleCode Decomposition and Recomposition for Enhancing Embedded Software Performance
Author*Youngchul Cho (SAIT, Samsung Electoronics, Republic of Korea), Kiyoung Choi (Seoul National University, Republic of Korea)
Pagepp. 624 - 629
Keywordcode transformation, code decomposition and recomposition, control-flow analysis, multitasking, code serialization
AbstractMultitasking of concurrent processes implements the concurrency inherited from applications, increasing the utilization of limited resources. It requires an operating system and imposes significant runtime overhead. Serializing multitasking codes removes the need of operating system and the overhead as well. In this paper, we propose a software synthesis method to transform multitasking codes into a single process code. For this, we decompose multitasking codes into a set of code fractions and then recompose the code fractions into a single process code, preserving the functionality of the original codes. We present two different techniques for the transformation - code partitioning and code covering - and propose a hybrid technique that combines the two techniques.