| Title | Fast False Path Identification Based on Functional Unsensitizability Using RTL Information |
| Author | *Yuki Yoshikawa (Hiroshima City University, Japan), Satoshi Ohtake (Nara Institute of Science and Technology, Japan), Tomoo Inoue (Hiroshima City University, Japan), Hideo Fujiwara (Nara Institute of Science and Technology, Japan) |
| Page | pp. 660 - 665 |
| Keyword | Delay test, False path, RTL, Over-testing reduction |
| Abstract | In this paper, we propose a method for identifying false paths based on functional unsensitizability of path delay faults. By using RTL structural information, a number of gate level paths are bound into an RTL path and the bundle of them can be identified in a reasonable amount of time. The identified false paths are useful for over-testing reduction caused by DFT techniques, such as scan design, and also area and performance optimization of circuits during logic synthesis. Experimental results show that our proposed method can identify false paths in a few seconds for several benchmarks. |
| Slides |
| Title | Conflict Driven Scan Chain Configuration for High Transition Fault Coverage and Low Test Power |
| Author | *Zhen Chen, Boxue Yin, Dong Xiang (Tsinghua University, China) |
| Page | pp. 666 - 671 |
| Keyword | broadside, fault coverage, low power, conflict |
| Abstract | Two conflict driven methods and the architecture based on them are presented to improve the fault coverage and reduce test power. By the analysis of the functional dependency of test vectors in broad-side and the shift dependency of vectors in the skewed-load, some scan cells are selected to operate in the enhanced scan and skewed-load scan mode, while others operate in traditional broad-side mode. Experimental results show that the fault coverage can achieve the level very close to enhanced scan. |
| Slides |
| Title | Dynamic Test Compaction for a Random Test Generation Procedure with Input Cube Avoidance |
| Author | Irith Pomeranz (Purdue University, United States), *Sudhakar Reddy (University of Iowa, United States) |
| Page | pp. 672 - 677 |
| Keyword | dynamic test compaction, test generation, stuck-at faults, full-scan |
| Abstract | A recent approach to test generation avoids the assignment of certain input values in order not to prevent target faults from being detected. The test generation process based on this approach is efficient; however, it generates large test sets. We develop a dynamic test compaction procedure for this approach. Our goal is to reduce the test set size by increasing the number of faults detected by each test vector, while keeping the computational complexity as low as that of the original procedure. This is achieved by avoiding the assignment of certain input values in order not to prevent subsets of faults from being detected. |
| Title | Detectability of Internal Bridging Faults in Scan Chains |
| Author | *Fan Yang (University of Iowa, United States), Sreejit Chakravarty, Narendra Devta-Prasanna (LSI Corp., United States), Sudhakar M. Reddy (University of Iowa, United States), Irith Pomeranz (Purdue University, United States) |
| Page | pp. 678 - 683 |
| Keyword | scan chain, bridge fault, resistive bridge, internal fault, non-feedback bridge |
| Abstract | We investigate the detection of scan cell internal bridging faults extracted from layout. We show that detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. Half-speed flush tests we proposed earlier detect additional bridging faults. Undetectable faults are classified based on the reasons for their undetectability. Both non-resistive and resistive bridging fault models are considered in this work. A low power supply voltage based test method and IDDQ testing are examined for resistive bridging fault detection. |
| Title | Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs |
| Author | *Bing-Chuan Bai (Department of Electrical Engineering, National Taiwan University, Taiwan), Augusli Kifli (Design Development Division, Faraday Technology Corporation, Taiwan), Chien-Mo Li (Department of Electrical Engineering, National Taiwan University, Taiwan), Kun-Cheng Wu (Design Development Division, Faraday Technology Corporation, Taiwan) |
| Page | pp. 684 - 689 |
| Keyword | Retention, Fault Model, low power, ATPG, Testing |
| Abstract | Retention flip-flop is one of the most important components in low power designs. This paper presents four new fault models of retention flip-flop. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Test patterns for retention flip-flop can be easily generated by ATPG tools. The proposed test methodology is validated by performing experiments on ISCAS’89 benchmark circuits and industrial designs. The experimental results show that average fault coverage is 98%. |