| Title | A Novel Toffoli Network Synthesis Algorithm for Reversible Logic |
| Author | *Yexin Zheng, Chao Huang (Virginia Tech, United States) |
| Page | pp. 739 - 744 |
| Keyword | reversible logic, quantum computing, logic synthesis |
| Abstract | Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input output correspondence which makes the logic synthesis for reversible functions differs greatly from traditional Boolean functions. Exact synthesis methods can provide optimal solutions in terms of the total number of reversible gates in the synthesis results. Unfortunately, they may suffer from long computation time, due to the fact that the search space is likely to grow exponentially as the circuit size increases. Therefore, in this paper, we propose an efficient synthesis heuristic which provides high quality synthesis results of Toffoli network in more reasonable computation time. We use a weighted, directed graph for reversible function representation and complexity measurement. The proposed algorithm maximally decreases function complexity during synthesis steps. It has the ability to climb out of local minimums and guarantees algorithm convergence. The experimental results show that our algorithm can achieve optimal or very close to optimal solutions with computation time several orders of magnitude less than the exact methods. Compared with other heuristics, our method demonstrates superior performance in terms of reversible gate count as well as computation time. |
| Title | A Cycle-Based Synthesis Algorithm for Reversible Logic |
| Author | *Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani (Amirkabir University of Technology, Iran) |
| Page | pp. 745 - 750 |
| Keyword | Reversible Logic, Cycle, NCT Library |
| Abstract | Abstract - Several algorithms have been proposed for the synthesis of reversible circuits. In this paper, a cycle-based synthesis algorithm for reversible logic, based on the NCT library, has been proposed. In other words, direct implementation of a single 3-cycle, a pair of 3-cycles and a pair of 2-cycles have been explored and used to propose an efficient Toffoli-based synthesis algorithm for reversible circuits. The synthesis algorithm decomposes a given large cycle into a set of single 3-cycles, pairs of 3-cycles and pair of 2-cycles and synthesizes the resulted cycles directly. Our experimental results show that the proposed synthesis algorithm can outperform the available 2-cycle-based approach about 34% on average. In addition, several discussions for the generalization of the proposed method to the 2m-cycles are given. |
| Slides | |
| Title | Array Like Runtime Reconfigurable MIMO Detectors for 802.11n WLAN: A Design Case Study |
| Author | Pankaj Bhagawat, Rajballav Dash, *Gwan Choi (Texas A&M University, United States) |
| Page | pp. 751 - 756 |
| Keyword | MIMO systems, 802.11n, Reconfigurability |
| Abstract | Future high speed wireless standards such as 802.11n involve Multiple Input Multiple Output (MIMO) antenna systems as a key technology component. Efficient design of the MIMO detector is a challenging task. This is further compounded by the fact that 802.11n standard requires support for runtime switching between different modulation schemes (or modes). While searching for an appropriate architecture attention must be paid to application requirements such as required throughput,limits on latency, and reconfiguration between various modes of operations. Important hardware design metrics such as area/power should be optimized over all the operating modes of the detector. In this paper we carry out extensive architectural space exploration to address the issues of power consumption,area, and reconfigurability between different modes of operation while meeting the standards throughput requirement. Ultimately, we come up with two designs that target low area and low power respectively. We also maintain close to optimum Bit Error Rate(BER), which is vital for any wireless system. The design estimates are based on 45nm technology library. |
| Slides | |
| Title | Mapping method for Dynamically Reconfigurable Architecture |
| Author | *Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano (Toshiba Corporation, Japan) |
| Page | pp. 757 - 762 |
| Keyword | dynamically reconfiguarable architecture, compiler, mapping |
| Abstract | In this paper, we present a mapping algorithm for our dynamically reconfigurable architecture which is suitable for stream applications such as H.264. Because our target architecture consists of four different configuration format units heterogeneously, itfs difficult to apply the conventional algorithms. We propose heuristic mapping algorithm which enables to map generic data flow graph onto this complex hardware automatically. We mapped five main functions of H.264 decoder onto our architecture and compared against manual-mapped result which is done by experienced engineer. The result shows that three of five functions are optimized as manual-mapping. |
| Title | A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner |
| Author | Srinath Sridharan, *Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan (Pennsylvania State University, United States) |
| Page | pp. 763 - 768 |
| Keyword | 3D IC, 3D architecture |
| Abstract | As technology scales, interconnect delay starts to dominate the performance of modern microprocessors. Three dimensional (3D) chip structures have been proposed as a solution to mitigate the interconnect challenge, with the capability of reducing global wiring lengths. Previous works on 3D microprocessor floorplanning have demonstrated the benefits of such wire reductions. However, in modern microprocessors, not all the global interconnects are equally important: some are critical for the performance and hence the wire reduction via 3D stacking can result in great performance improvement, while others may not be on the critical path and therefore the wire reduction may not have impact on the performance. In this paper, we propose a floorplanner for 3D chips that will organize functional blocks according to critical microarchitectural communication paths in order to reduce latencies which will hinder processor performance. We identify potential triggers, in the form of feedback delays, that are responsible for incurring high communication costs and curb its negative effect on performance by intelligently placing the functional blocks in 3D without compromising on area, overlap power density and thermal reliability. With our criticality driven 3D, placement there is an IPC improvement on an average 22% and up to a 64% improvement over 2D placement. Over criticality un-aware 3D placement, criticality driven 3D placement shows an IPC improvement on an average of 8% and up to 25%. |