| Title | High-Speed Low-Power FinFET Based Domino Logic |
| Author | Seid Hadi Rasouli (University of California, Santa Barbara, United States), Hanpei Koike (Electroinformatics Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Japan), *Kaustav Banerjee (University of California, Santa Barbara, United States) |
| Page | pp. 829 - 834 |
| Keyword | FinFET, high speed, low power, domino logic, resistive gate |
| Abstract | This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the pull-down network, but gradually becomes stronger to provide high noise margin. |
| Title | A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories |
| Author | *M. Haykel Ben Jamaa (Ecole Polytechnique Federale de Lausanne, Switzerland), David Atienza (Universidad Complutense de Madrid, Spain), Yusuf Leblebici, Giovanni De Micheli (Ecole Polytechnique Federale de Lausanne, Switzerland) |
| Page | pp. 835 - 840 |
| Keyword | nanotechnology, crossbar memories, reliability, nanowires |
| Abstract | The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correct operation. In particular, the variability affecting the decoder is expected to make very complex the test of these new devices. In this paper we present a method to simplify the test of these new devices by using a current thresholder to detect badly addressed nanowires. In the proposed method, the thresholder design is based on a stochastic and perturbative model of the current through the nanowires. Thus, the calculated thresholder parameters are robust against technology variation. As our experimental results indicate, the thresholder error probability is initially only 104, which can be also reduced further (up to 60x) by trading-off only 35% area overhead in the memory. |
| Slides | |
| Title | An Alternate Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective |
| Author | Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, *Kaushik Roy (Purdue University, United States) |
| Page | pp. 841 - 846 |
| Keyword | Spintronics, MRAM, yield |
| Abstract | Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough analysis of the impact of design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an alternate design paradigm —circuit/architecture co-design — to take advantage of different levels of design hierarchy (circuit and architecture) to improve the yield and memory density. The technique decouples the conflicting design requirements for read stability/writability and density. Consequently, the memory cell failure probability reduces by 48% and cell area reduces by 21% with negligible performance degradation (~0.4%). |
| Title | A Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems |
| Author | Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, *Kaushik Roy (Purdue University, United States) |
| Page | pp. 847 - 852 |
| Keyword | MQCA, Design Methodology, Simulation Framework, low power, CMOS alternative |
| Abstract | CMOS device scaling is facing a daunting challenge with increased parameter variations and exponentially higher leakage current every new technology generation. Thus, researchers have started looking at alternative technologies. Magnetic Quantum Cellular Automata (MQCA) is such an alternative with switching energy close to thermal limits and scalability down to 5nm. In this paper, we present a circuit/architecture design methodology using MQCA. Novel clocking techniques and strategies are developed to improve computation robustness of MQCA systems. We also developed an integrated device/circuit/system compatible simulation framework to evaluate the functionality and the architecture of an MQCA based system and conducted a feasibility/comparison study to determine the effectiveness of MQCAs in digital electronics. Simulation results of an 8-bit MQCA-based Discrete Cosine Transform (DCT) with novel clocking and architecture show up to 290X and 46X improvement (at iso-delay) over 45nm CMOS in energy consumed and area, respectively. |
| Title | Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture |
| Author | *Bao Liu (The University of Texas at San Antonio, United States) |
| Page | pp. 853 - 858 |
| Keyword | carbon nanotube, nanoelectronic architecture |
| Abstract | Carbon nanotubes (CNTs) and carbon nanotube field effect transistor (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. However, no nanoelectronic architecture has been proposed which is solely based on carbon nanotubes and carbon nanotube field effect transistors. In this paper, I propose a novel double gate carbon nanotube field effect transistor (RDG-CNFET), which is reconfigurable to be open, short, FET, or via. Layers of orthogonal carbon nanotubes with electrically bistable molecules sandwiched at each crossing form a dense array of RDG-CNFETs and programmable interconnects, and constitute a nanoelectronic architecture of manufacturability (via regularity), reliability (via reconfigurability), and performance (via device density). Simulation based on CNFET and molecular device compact models demonstrates superior logic density, reliability, performance and power consumption of the proposed RDG-CNFET based nanoelectronic circuits compared with the existing, e.g., molecular diode/MOSTFET based nanoelectronic circuits. |