| Title | Hybrid Dynamic Energy and Thermal Management in Heterogeneous Embedded Multiprocessor SoCs |
| Author | Shervin Sharifi, Ayse Kivilcim Coskun, *Tajana Simunic Rosing (University of California, San Diego, U.S.A.) |
| Page | pp. 873 - 878 |
| Keyword | Temperature, Thermal, Embedded Systems, Multiprocessor SoC, Heterogeneous |
| Abstract | Heterogeneous multiprocessor system-on-chips
(MPSoCs) which consist of cores with various power and
performance characteristics can customize their configuration
to achieve higher performance per Watt. On the other hand,
inherent imbalance in power densities across MPSoCs leads to
non-uniform temperature distributions, which affect
performance and reliability adversely. In addition, managing
temperature might result in conflicting decisions with achieving
higher energy efficiency. In this work, we propose a joint
thermal and energy management technique specifically designed
for heterogeneous MPSoCs. Our technique identifies the
performance demands of the current workload. By utilizing job
scheduling and voltage/frequency scaling dynamically, we meet
the desired performance while minimizing the energy
consumption and the thermal imbalance. In comparison to
performance-aware policies such as load balancing, our
technique simultaneously reduces the thermal hot spots,
temperature gradients, and energy consumption significantly. |
| Slides |
| Title | Energy Efficient Joint Scheduling and Multi-core Interconnect Design |
| Author | Cathy Qun Xu (University of Texas at Dallas, U.S.A.), *Chun Jason Xue (City University of Hong Kong, China), Yi He, Edwin H.M. Sha (University of Texas at Dallas, U.S.A.) |
| Page | pp. 879 - 884 |
| Keyword | Scheduling, Interconnection network, Low power |
| Abstract | Energy efficient and high performance interconnect is critical
for multi-core architecture.Interconnect with power saving segmented buses satisfies the tight latency and high volumn data transfer needs of applications with large embeded pallelism.
This paper analyzes the major energy consumption factors of interconnect with segmented buses from high level synthesis.
It presents a computation and inter-core data transfer scheduling algorithm to minimize the interconnect energy consumption by addressing the analyzed factors while exploring an application's maximum parallelism. This paper jointly considers scheduling and interconnect design. It presents an application specific approach
to determine the minimum number of segmented buses required and an optimal inter core data transfer schedule which can be used to configure the switches on the segmented buses to avoid bus contention and minimize interconnect energy consumption with
a given application. Experimental results show that the proposed scheduling algorithm can reduce interconnect dynamic energy
consumption about 71% and static energy consumption about 23% on average compared to the other communication cost conscious scheduling techniques for evaluated high parallelism DSP applications. |
| Slides |
| Title | Dynamic and Adaptive Allocation of Applications on MPSoC Platforms. |
| Author | *Andreas Schranzhofer, Jian-Jia Chen (Swiss Federal Institute of Technology (ETH), Zürich, Switzerland), Luca Santinelli (Scuola Superiore Sant'Anna, Pisa, Italy), Lothar Thiele (Swiss Federal Institute of Technology (ETH), Zürich, Switzerland) |
| Page | pp. 885 - 890 |
| Keyword | MPSoC, multi-mode application, mapping, dynamic, adaptive |
| Abstract | Multi-Processor Systems-on-Chip (MPSoC) are an increasingly important design paradigm not only for mobile embedded systems but also for industrial applications such as automotive and avionic systems. Such systems typically execute multiple concurrent applications, with different execution modes. Modes define differences in functionality and computational resource demands and are assigned with an execution probability. We propose a dynamic mapping approach to maintain low power consumption over the system lifetime. Mapping templates for different application modes and execution probabilities are computed offline and stored on the system. At runtime a manager monitors the system and chooses an appropriate pre-computed template. Experiments show that our approach outperforms global static mapping approaches up to 45%. |
| Slides |