| Title | A PUF Design for Secure FPGA-Based Embedded Systems |
| Author | *Jason H. Anderson (University of Toronto, Canada) |
| Page | pp. 1 - 6 |
| Keyword | Embedded systems, hardware security, FPGAs, PUF, IC counterfeiting |
| Abstract | The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counterpiracy. Physically unclonable functions (PUFs) are circuits that compute a unique signature for a given IC based on the process variations inherent in the IC manufacturing process. This paper presents the first PUF design specifically targeted for field-programmable gate arrays (FPGAs). Our novel design makes use of the underlying FPGA architecture, and unlike prior published PUFs, the proposed PUF can be naturally embedded into a design’s HDL, consuming very little area, and does not require the use of “hard macros” with fixed routing. Measured results on the Xilinx Virtex-5 65 nm FPGA demonstrate PUF signatures to be both unique and reliable under temperature variation. |
| Slides | |
| Title | Adaptive Power Management for Real-Time Event Streams |
| Author | *Kai Huang (ETH Zurich, Switzerland), Luca Santinelli (Scuola Superiore Sant'Anna of Pisa, Italy), Jian-Jia Chen, Lothar Thiele (ETH Zurich, Switzerland), Giorgio C. Buttazzo (Scuola Superiore Sant'Anna of Pisa, Italy) |
| Page | pp. 7 - 12 |
| Keyword | Adaptive Power Management, Energy Minimization, Real-Time Event Streams, Real-Time Calculus |
| Abstract | Dynamic power management has become essential for battery-driven embedded systems. This paper explores how to efficiently and effectively reduce the energy consumption of a device (system) for serving multiple event streams under hard real-time constraints. Considering two different preemptive scheduling, i.e., earliest deadline first and fixed priority, we propose algorithms to adaptively control the power mode of the device according to historical arrivals of events. Our algorithms can not only tackle arbitrary event arrivals but also provide hard real-time guarantees with respect to both timing and backlog constraints. We also present simulation results to demonstrate the effectiveness of our approaches. |
| Slides | |
| Title | An Alternative Polychronous Model and Synthesis Methodology for Model-Driven Embedded Software |
| Author | Bijoy Antony Jose, *Sandeep Kumar Shukla (FERMAT Lab, Virginia Tech, U.S.A.) |
| Page | pp. 13 - 18 |
| Keyword | Embedded Software, Polychrony, Model-driven software, code synthesis |
| Abstract | Multi-clocked synchronous (a.k.a. Polychronous) specification languages do not assume that execution proceeds by sampling inputs at predetermined global synchronization points. The software synthesized from such specifications are paced by arrival of certain inputs, or evaluation of certain internal variables. Here, we present an alternate polychronous model of computation termedMulti-rate Instantaneous Channel connected Data Flow (MRICDF) actor network model. Sequential embedded software from MRICDF specifications can be synthesized using epoch analysis, a technique proposed to form a unique order of events without a reference time line. We show how to decide on the implementability of MRICDF specification and how additional epoch information can help in synthesizing deterministic sequential software. The semantics of an MRICDF is akin to that of SIGNAL, but is visual and easier to specify. Also, our prime implicate based epoch analysis technique avoids the complex clocktree based analysis required in SIGNAL. We experimented with the usability of MRICDF formalism by creating EmCodeSyn, our visual specification and synthesis tool. Our attempt is to make polychronous specification based software synthesis more accessible to engineers, by proposing this alternativemodel with different semantic exposition and simpler analysis techniques. |
| Slides | |
| Title | Trace-based Performance Analysis Framework for Heterogeneous Multicore Systems |
| Author | Shih-Hao Hung, *Chia-Heng Tu, Thean-Siew Soon (National Taiwan University, Taiwan) |
| Page | pp. 19 - 24 |
| Keyword | Performance analysis tool, heterogeneous multicore platform, trace-based performance analysis |
| Abstract | Performance evaluation is key to the optimization of computer applications on multicore systems. While many techniques and profiling tools are available for measuring performance on homogeneous multicore platforms, most of them depend on the hardware support from the vendors. For developing applications on heterogeneous multicore systems, very few analysis tools exist to help the developers. This paper describes a software-based trace collection and performance analysis framework that can be ported to a variety of platforms via code instrumentation at the source level. A pure software profiling toolkit, called ParallelTracer, were implemented based on ANTLR, an open source parser generator, to support this framework. In this paper, we present our framework and toolkit. We use the IBM Cell processor as a case study to demonstrate the capability of ParallelTrace. Our results show that ParallelTracer provided useful information for programmers to understand program behaviors and identify potential performance bottlenecks via graphical visualization. We also discuss the runtime overhead of ParallelTracer. With proper usage, the performance and code size overhead introduced by our toolkit are limited around 19% to 5% and 9%, respectively, for the benchmark program in the case study. |
| Slides | |