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The 15th Asia and South Pacific Design Automation Conference

Session 1C  Logic Synthesis
Time: 13:30 - 15:10 Tuesday, January 19, 2010
Location: Room 101C
Chairs: Yuan Xie (Pennsylvania State Univ., U.S.A.), Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)

1C-1 (Time: 13:30 - 13:55)
TitleSimultaneous Slack Budgeting and Retiming for Synchronous Circuits Optimization
Author*Shenghua Liu, Yuchun Ma, Xian-Long Hong, Yu Wang (Tsinghua Univ., China)
Pagepp. 49 - 54
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1C-2 (Time: 13:55 - 14:20)
TitleA Fast SPFD-based Rewiring Technique
Author*Pongstorn Maidee, Kia Bazargan (Univ. of Minnesota, U.S.A.)
Pagepp. 55 - 60
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1C-3 (Time: 14:20 - 14:45)
TitleiRetILP: An Efficient Incremental Algorithm for Min-period Retiming under General Delay Model
AuthorDebasish Das (Northwestern Univ., U.S.A.), Jia Wang (Illinois Inst. of Tech., U.S.A.), *Hai Zhou (Northwestern Univ., U.S.A.)
Pagepp. 61 - 67
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