| Title | Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling |
| Author | Kuen-Huei Lin, Siao-Jie Cai, *Chung-Yang (Ric) Huang (National Taiwan University, Taiwan) |
| Page | pp. 143 - 148 |
| Keyword | Virtual platform simulation, data-dependency-aware, virtual synchronization, trace-driven simulation |
| Abstract | In this paper, we proposed a novel simulation scheme, called data-dependency-aware synchronization and scheduling, for SoC virtual platform simulation. In contrast to the conventional clock- or transaction-based synchronization, our simulation scheme can work with the clock decoupling and direct-data-access techniques to implement the trace-driven virtual synchronization methodology. In addition, we further extend the virtual synchronization concept to handle the interrupt signals in the system. This enables the porting of operating system (uCLinux) in our virtual platform. The experimental results show that our virtual platform can achieve 3 to 5 million-instructions-per-second simulation speed, or 44 times speed-up over the conventional cycle accurate approach, while still maintaining the same cycle-count accuracy. |
| Title | SCGPSim: A Fast SystemC Simulator on GPUs |
| Author | Mahesh Nanjundappa (FERMAT LAB, Virginia Polytechnic Institute and State University, U.S.A.), Hiren D Patel (Department of ECE, University of Waterloo, Canada), Bijoy A Jose, *Sandeep K Shukla (FERMAT LAB, Virginia Polytechnic Institute and State University, U.S.A.) |
| Page | pp. 149 - 154 |
| Keyword | GPGPU, SystemC, CUDA, Parallel Simulation |
| Abstract | The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level by exploiting the high degree of parallelism afforded by today's general purpose graphics processors (GPGPUs). Our approach parallelizes SystemC's discrete-event simulation (DES) on GPGPUs by transforming the model of computation of DES into a model of concurrent threads that synchronize as and when necessary. Unlike the cooperative threading model employed in the SystemC reference implementation, our threading model is capable of executing in parallel on the large number of simple processing units available on GPUs. Our simulation infrastructure is called SCGPSim and it includes a source-to-source (S2S) translator to transform synthesizable SystemC models into parallelly executable programs targeting an NVIDIA GPU. The translator retains the simulation semantics of the original designs by applying semantics preserving transformations. The resulting transformed models mapped onto the massively parallel architecture of GPUs improve simulation efficiency quite substantially. Preliminary experiments with varying-sized examples such as AES, ALU, and FIR have shown simulation speed-ups ranging from 30x to 100x. Considering that our transformations are not yet optimized, we believe that optimizing them will improve the simulation performance even further. |
| Slides |
| Title | A Flexible Hybrid Simulation Platform Targeting Multiple Configurable Processors SoC |
| Author | *Hao Shen, Frédéric Pétrot (TIMA Laboratory, INP Grenoble, France) |
| Page | pp. 155 - 160 |
| Keyword | semi-hosting, hybrid, simulation, MPSoC, configurable processor |
| Abstract | Multiple Configurable Processors System-on-Chip
(MCPSoC) platforms have both performance and power advantages
for embedded applications. Unfortunately, at early design
stages, because of the processor configuration, I/O device changes
and MCPSoC architecture modifications, designers waste much
time on the Operating System (OS) porting work with general
Instruction Set Simulator (ISS) based SoC simulation platforms.
In this paper, we propose a hybrid simulation platform which
uses general ISS and implements the Hardware Abstraction
Layer (HAL) Application Programming Interfaces (APIs) and
I/O device driver APIs with the SystemC modules on host
machines directly. This hybrid simulation platform can shorten
the application validation process by avoiding assembly code and
hard-coded address modifications of traditional OS porting work.
We show the advantages of our new hybrid simulation platform
with a video decoding case study in the end. |
| Slides |
| Title | A Fast Heuristic Scheduling Algorithm for Periodic ConcurrenC Models |
| Author | *Weiwei Chen, Rainer Doemer (Center for Embedded Computer Systems, University of California, Irvine, U.S.A.) |
| Page | pp. 161 - 166 |
| Keyword | ConcurrenC, Static Scheduling, Model of Computation, System Level Description Language |
| Abstract | Embedded system design usually starts from an executable specification model described in a C-based System Level Description Language (SLDL), such as SystemC or SpecC. In this paper, we identify a subset of well-defined C-based design models, called periodic ConcurrenC models, that can be statically scheduled, resulting in significant higher simulation and execution speed. We propose a novel heuristic scheduling algorithm that not only is faster than classic matrix-based synchronous data flow (SDF) scheduling approaches, but also reduces the model execution time by an order of magnitude over the default discrete event simulation. |
| Slides |