| Title | Analyzing Electrical Effects of RTA-driven Local Anneal Temperature Variation |
| Author | *Vivek Joshi (University of Michigan, U.S.A.), Kanak Agarwal (IBM Austin Research Lab, U.S.A.), Dennis Sylvester, David Blaauw (University of Michigan, U.S.A.) |
| Page | pp. 739 - 744 |
| Keyword | RTA, thermal analysis, Performance, Leakage |
| Abstract | Suppresing device leakage while maximizing drive
current is the prime focus of semiconductor industry. Rapid
Thermal Annealing (RTA) drives process development on this
front by enabling fabrication steps such as shallow juction formation
that require a low thermal budget. However, the decrease
in junction anneal time for more aggresive device scaling has
reduced the characteristic thermal length to dimensions less than
the typical die size. Also, the amount of heat transferred, and
hence the local anneal temperature, is affected by the layout pattern
dependence of optical properties in a region. This variation
in local anneal temperature causes a variation in performance
and leakage across the chip by affecting the threshold voltage
(Vth) and extrinsic transistor resistance (Rext). In this work, we
propose a new local anneal temperature variation aware analysis
framework which incorporates the effect of RTA induced temperature
variation into timing and leakage analysis. We solve for
chip level anneal temperature distribution, and employ TCAD
based device level models for drive current (Ion) and leakage
current (Ioff) dependence on anneal temperature variation, to
capture the variation in device performance and leakage based on
its position in the layout. Experimental results based on a 45nm
experimental test chip shows anneal temperature variations of up
to 10.5oC, which results in ~6.8% variation in device performance
and 2.45X variation in device leakage across the chips.
The corresponding variation in inverter delay was found to be
~7.3%. The temperature variation for a 65nm test chip was found
to be ~8.65oC. |
| Slides |
| Title | Physical Design Techniques for Optimizing RTA-induced Variations |
| Author | Yaoguang Wei (University of Minnesota, U.S.A.), Jiang Hu (Texas A&M University, U.S.A.), Frank Liu (IBM Austin Research Lab, U.S.A.), *Sachin Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 745 - 750 |
| Keyword | rapid thermal annealing, dummy fill, floorplanning |
| Abstract | At 65nm and below, Rapid Thermal Annealing (RTA) makes a significant
contribution to manufacturing process variations, degrading the
parametric yield. RTA-induced variability strongly depends on circuit
layout patterns, particularly the distribution of the density of the
Shallow Trench Isolation (STI) regions. In this work, we investigate a
two-step approach to reduce the impact of RTA-induced variations. We
first solve a floorplanning problem that aims to reduce the RTA
variations by evening out the STI density distribution. Next, we insert
dummy polysilicon fills to further improve the uniformity of the STI
density. Experimental results show that our floorplanner can reduce the global RTA variations by 39% and the local variations by 29% on average with low overhead compared to a traditional floorplanner, and the proposed dummy fill algorithm can further reduce the RTA variations to negligible amounts. Moreover, when inserting dummy fills, for the layouts obtained by our floorplanner, on average, 24% fewer dummy polysilicon fills are
inserted, as compared to the results from a traditional floorplanner. |
| Slides |
| Title | On Confidence in Characterization and Application of Variation Models |
| Author | Lerong Cheng, Puneet Gupta, *Lei He (UCLA, U.S.A.) |
| Page | pp. 751 - 756 |
| Keyword | variation, confidence interval |
| Abstract | In this paper we study statistics of statistics. Due to limited number of samples (especially in the case of lot-to-lot variation), calibrated models have low degree of confidence. The problem is further exacerbated when production volumes are low (< 65 lots) causing additional loss of confidence in the statistical analysis (since production only sees a small snapshot of the entire distribution). We mathematically derive the confidence intervals for commonly used statistical measures (mean, variance, percentile corner) and analysis (SPICE corner extraction, statistical timing). Our estimates are within 2% of simulated confidence values. Our experiments (with variability assumptions derived from test silicon data from a 45nm industrial process) indicate that for moderate characterization volumes (10 lots) and low-to-medium production volumes (15 lots), a significant guardband (e.g., 34.7% of standard deviation for single parameter corner, 38.7% of standard deviation for SPICE corner, and 52% of standard deviation for 95%-tile point of circuit delay) is needed to ensure 95% confidence in the results. The guardbands are non-negligible for all cases when either production or characterization volume is not large. The proposed methods require are not runtime-intensive (always within 10s) as they require
Monte-Carlo simulations on closed form expressions. |