| Title | Incremental Solution of Power Grids using Random Walks |
| Author | *Baktash Boghrati, Sachin S. Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 757 - 762 |
| Keyword | power grid, random walk, linear equation solver, incremental analysis |
| Abstract | It is common for a designer to make multiple small changes to a power grid, corresponding to "what if" scenarios, in an attempt to improve its performance. To evaluate the effects of this incremental change, the circuit may go through incremental analysis. This paper presents a computationally efficient and accurate method for fast and accurate incremental analysis, using random walks to identify a region of influence (RoI) of a change, so that this RoI can then be analyzed by any other solver. Our experimental results demonstrate the accuracy and computational efficiency of this method. |
| Slides |
| Title | Efficient Power Grid Integrity Analysis Using On-the-Fly Error Check and Reduction |
| Author | Duo Li, *Sheldon Tan, Ning Mi (University of California, Riverside, U.S.A.), Yici Cai (Tsinghua University, China) |
| Page | pp. 763 - 768 |
| Keyword | power grid analysis, model order reduction, truncated balanced realization, IR drop analysis |
| Abstract | In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reduction technique to reduce the circuit matrices before the simulation. Due to the disruptive nature of tap current waveforms in typical industry power grid networks, input current sources typically has wide frequency power spectrum. To avoid the excessively sampling, the new approach introduces an error check mechanism and on-the-fly error reduction scheme during the simulation of the reduced circuits to improve the accuracy of estimating the the large IR drops. The proposed method presents a new way to combine model order reduction and simulation to achieve the overall efficiency of simulation. The new method can also easily trade errors for speed for different applications. Experimental results show the proposed IR drop analysis method can significantly reduce the errors of the existing ETBR method at the similar computing cost, while it can have 10X and more speedup over the the commercial power grid simulator in UltraSim with about 1-2% errors on a number of real industry benchmark circuits. |
| Title | PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization |
| Author | Li Li (WuHan University of Technology, China), *Yuchun Ma (Tsinghua Univ., China), Ning Xu (WuHan University of Technology, China), Yu Wang, Xianlong Hong (Tsinghua Univ., China) |
| Page | pp. 769 - 774 |
| Keyword | P/G network, Floorplanning, Wiring resource |
| Abstract | As technology advances, the voltage (IR) drop in the Power/Ground (P/G) network becomes a serious problem in modern IC design. The P/G network co-design with floorplan can improve the power design quality. Different with traditional approaches which analyze P/G network during the floorplanning iterations, in this paper, an efficient pattern selection method is used to provide gradient information for fast signal-integrity estimation. We also propose a novel P/G aware incremental algorithm which can intelligently fix the violations during the floorplanning process. The P/G pin assignment and wire sizing method are adopted during the floorplanning process so that the power routing resource can be minimized with the constraints of IR drop and electron migration (EM) considered. Experimental results based on the MCNC benchmarks show that our design not only significantly speeds up the optimization process, but also optimizes the power routing resource while the quality of the floorplanning is maintained. |