| Title | (Invited Paper) -Possibility of ESL- A Software Centric System Design for Multicore SoC in the Upstream Phase |
| Author | *Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan) |
| Page | pp. 805 - 808 |
| Keyword | Multi-core system, Parallel software, SMP, Linux, Symbian, Unix and RealTime OS, Multimedia |
| Abstract | The embedded systems for which both hardware and software are rapidly advancing and expanding, there is a growing need to be able to comprehensively and quantitatively estimate system performance at an early stage in the design process, especially multi-core based SoC. But it can be difficult to estimate system performance of actual target by employing only simple estimation methods. By using ESL technology, without implemented hardware, that enables high-precision assessment of system performance with software that runs on OS. By applying proposed assessment environment during upstream design of target system, it enables to research the characteristics of performance, bottle-neck and avoid the risk of the re-design. It will be the key-issue of ESL methodology. It might be tightly related with software architecture and it is different point of view from typical upstream design of hardware. |
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| Title | (Invited Paper) Design of Complex Image Processing Systems in ESL |
| Author | Benjamin Carrion Schafer (NEC Corporation, Japan), Ashish Trambadia (NECHCL ST, Japan), *Kazutoshi Wakabayashi (NEC Corporation, Japan) |
| Page | pp. 809 - 814 |
| Keyword | ESL, C, synthesis, image processing, design space exploration |
| Abstract | This work presents the design of a complex image processing IP developed completely in C. We present the latest advanced in ESL-synthesis and demonstrate its main advantages over conventional RT-level flows. In particular we focus on the ability of behavioral synthesis to shorten the design cycle, perform functional verification and explore quickly the design space obtaining multiple dominating implementations with unique area vs. speed characteristics from an initial untimed behavioral description. A feature extraction process is presented in detailed showing how automatic design space exploration can lead to Pareto optimal (non-dominant) designs ranging from 524,648 gates to 584,868 gates and latencies of 38 to 69 state counts for the smallest and fastest design respectively taking approximately 6.3 hours. |
| Title | (Invited Paper) PAC Duo System Power Estimation at ESL |
| Author | *Wen-Tsan Hsieh, Jen-Chieh Yeh (Industrial Technology Research Institute, Taiwan), Shi-Yu Huang (TinnoTek Corp./National Tsing Hua Univ., Taiwan) |
| Page | pp. 815 - 820 |
| Keyword | ESL power estimation, ESL power analysis |
| Abstract | In this work, we develop an electronic system-level (ESL) power estimation framework which uses the specified power model interface. Using the proposed power model interface we can easily integrate the various power models in ESL virtual platform. Designers can choose either the coarse-grained or fine-grained power models according to the trade-off between accuracy and computing cost. The experimental results show the proposed method can accurate estimate the system power trend immediately compared with traditional method. We also demonstrated the capability of system power and performance analysis in both hardware-view and software-view by using our approach at ESL. Meanwhile, it can be used for high level architecture exploration directly. |
| Title | (Invited Paper) A Practice of ESL Verification Methodology from SystemC to FPGA -Using EPC Class-1 Generation-2 RFID Tag Design as An Example |
| Author | *William Young (TSMC, Taiwan), Chua-Huang Huang (Feng Chia University, Taiwan), Alan P. Su (Global Unichip Corp., Taiwan), C. P. Jou, Fu-Lung Hsueh (TSMC, Taiwan) |
| Page | pp. 821 - 824 |
| Keyword | ESL, verification methodology, SystemC, FPGA |
| Abstract | This paper presents the first published industrial practice (to the best of our knowledge) to reuse high-level/C++ system simulation model through OSCI TLM 2.0 Library to verify its corresponding RTL implementation in FPGA. ESL verification methodology is employed in the design regression of EPC C1Gen2 RFID tag. Around 200 times speedup is observed using ESL over conventional RTL simulation in regression runs (after logic bug fixes). This clearly shows ESL verification is a successful candidate to reuse high-level test harness for IC functional verification, especially in today's increasingly complex IC design world. On top of the successful use of the ESL functional verification flow on the design, we also show the infrastructure to use SystemC Verification Library (SCV) for formal verification. The functional and formal verification combined is thus the proposed ESL verification methodology. |
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