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The 18th Asia and South Pacific Design Automation Conference

Session 1A  Special Session: Advanced Modeling and Simulation Techniques for Power/Signal Integrity in 3D Design
Time: 10:20 - 12:20 Wednesday, January 23, 2013
Organizer: Hideki Asai (Shizuoka University, Japan)

1A-1 (Time: 10:20 - 10:50)
Title(Invited Paper) Equivalent Circuit Model Extraction for Interconnects in 3D ICs
Author*A. Ege Engin (San Diego State University, U.S.A.)
Pagepp. 1 - 6
KeywordTSV, 3D IC, silicon interposer
AbstractParasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs. Recent 3D ICs promise to reduce the parasitic RC effect by making use of through silicon vias (TSVs). It is therefore essential to extract the RC model of TSVs to assess their promise. Unlike interconnects on metal layers, TSVs exhibit slow-wave and dielectric quasi-transverse-electromagnetic (TEM) modes due to the coupling to the semiconducting substrate. This TSV behavior can be simulated using analytical methods, 2D electrostatic simulators, or 3D full-wave electromagnetic simulators. In this paper, we describe a methodology to extract parasitic RC models from such simulation data for interconnects in a 3D IC.

1A-2 (Time: 10:50 - 11:20)
Title(Invited Paper) Unconditionally Stable Explicit Method for the Fast 3-D Simulation of On-Chip Power Distribution Network with Through Silicon Via
Author*Tadatoshi Sekine, Hideki Asai (Shizuoka University, Japan)
Pagepp. 7 - 12
Keywordpower distribution network, through silicon via, explicit method, unconditionally stable, fast circuit simulation
AbstractIn this work, we propose the method which is explicit, but stable with no stability condition for the fast simulation of the equivalent circuit of on-chip power distribution network with a number of through silicon vias. Additionally, the proposed unconditionally stable explicit method is accelerated more by combining with an order reduction technique.

1A-3 (Time: 11:20 - 11:50)
Title(Invited Paper) Signal Integrity Modeling and Measurement of TSV in 3D IC
Author*Joungho Kim, Joungho Kim (Korea Advanced Institute of Science and Technology, Republic of Korea)
Pagepp. 13 - 16
KeywordThrough Silicon Via, Signal Integrity, Modeling, Measurement
AbstractIn order to guarantee signal integrity of a TSV-based channel in 3D IC design, the modeling and measurements are conducted for electrical characterization of the TSV-based channel including TSVs and RDLs with various performance metrics such as insertion loss, noise coupling and eye diagrams. Based on the modeling and measurements of the fabricated TSV channels, design guide for the signal integrity of the channel is proposed.

1A-4 (Time: 11:50 - 12:20)
Title(Invited Paper) Power Distribution Network Modeling for 3-D ICs with TSV Arrays
AuthorChi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, *Tzong-Lin Wu (National Taiwan University, Taiwan)
Pagepp. 17 - 22
Keyword3-D IC, PDN, equivalent circuit model, TSV, CNIM
AbstractA coupling node insertion method (CNIM) is proposed to handle electrical coupling between top metals of on-chip interconnects and silicon substrate surfaces in three-dimensional integrated circuits (3-D ICs). This coupling effect should not be neglected especially as metal area is intentionally increased in order to reduce resistance values. In this paper, we illustrate how to build the CNIM model and incorporate it into power distribution networks. The CNIM model is validated by comparing our results to the one obtained from a full-wave simulator. The differences between two approaches are within 5% but our computation time is shorter than that required by a full-wave simulator.