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The 18th Asia and South Pacific Design Automation Conference

Session 2D  Advanced Routing Techniques for Chip and PCB Design
Time: 13:40 - 15:40 Wednesday, January 23, 2013
Chairs: Toshiyuki Shibuya (Fujitsu Laboratory, Japan), Jai-Ming Lin (National Cheng Kung Univ., Taiwan)

2D-1 (Time: 13:40 - 14:10)
TitleA Separation and Minimum Wire Length Constrained Maze Routing Algorithm under Nanometer Wiring Rules
Author*Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak (National Tsing Hua Univ., Taiwan), Sheng-Hsiung Chen (Springsoft, Taiwan)
Pagepp. 175 - 180
Detailed information (abstract, keywords, etc)

2D-2 (Time: 14:10 - 14:40)
TitleAn ILP-based Automatic Bus Planner for Dense PCBs
AuthorPei-Ci Wu (Univ. of Illinois, Urbana-Champaign, U.S.A.), Qiang Ma (Synopsys, Inc., U.S.A.), *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 181 - 186
Detailed information (abstract, keywords, etc)

2D-3 (Time: 14:40 - 15:10)
TitleLayer Minimization in Escape Routing for Staggered-Pin-Array PCBs
Author*Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang (National Taiwan Univ., Taiwan), Chung-Kuan Cheng (Univ. of California, San Diego, U.S.A.)
Pagepp. 187 - 192
Detailed information (abstract, keywords, etc)

2D-4 (Time: 15:10 - 15:40)
TitleNetwork Flow Modeling for Escape Routing on Staggered Pin Arrays
AuthorPei-Ci Wu, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 193 - 198
Detailed information (abstract, keywords, etc)