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The 18th Asia and South Pacific Design Automation Conference

Session 8B  Revisiting Latency and Reliability in Memory Architectures
Time: 13:40 - 15:40 Friday, January 25, 2013
Chairs: Luca Carloni (Columbia Univ., U.S.A.), Fabien Clermidy (CEA-LETI, France)

8B-1 (Time: 13:40 - 14:10)
TitleReevaluating the Latency Claims of 3D Stacked Memories
Author*Daniel W. Chang (Univ. of Wisconsin, Madison, U.S.A.), Gyungsu Byun (West Virginia Univ., U.S.A.), Hoyoung Kim, Minwook Ahn, Soojung Ryu (Samsung Electronics Co., Ltd., Republic of Korea), Nam S. Kim, Michael Schulte (Univ. of Wisconsin, Madison, U.S.A.)
Pagepp. 657 - 662
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8B-2 (Time: 14:10 - 14:40)
TitleHeterogeneous Memory Management for 3D-DRAM and External DRAM with QoS
Author*Le-Nguyen Tran (Univ. of California, Irvine, U.S.A.), Houman Homayoun (George Mason Univ., U.S.A.), Fadi J. Kurdahi, Ahmed M. Eltawil (Univ. of California, Irvine, U.S.A.)
Pagepp. 663 - 668
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8B-3 (Time: 14:40 - 15:10)
TitleLine Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality
Author*Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ., Japan)
Pagepp. 669 - 674
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8B-4 (Time: 15:10 - 15:40)
TitleShieldUS: A Novel Design of Dynamic Shielding for Eliminating 3D TSV Crosstalk Coupling Noise
Author*Yuan-Ying Chang, Yoshi Shih-Chieh Huang (National Tsing Hua Univ., Taiwan), Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.), Chung-Ta King (National Tsing Hua Univ., Taiwan)
Pagepp. 675 - 680
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