| Title | Reconstruction of Memory Accesses Based on Memory Allocation Mechanism for Source-Level Simulation of Embedded Software |
| Author | *Kun Lu, Daniel Müller-Gritschneder, Ulf Schlichtmann (Technische Universität München, Germany) |
| Page | pp. 729 - 734 |
| Keyword | source level simulation, TLM, performance estimation |
| Abstract | To date, there still lacks a way to accurately simulate data memory accesses in source-level simulation (SLS) of host-compiled embedded SW. The difficulty lies in that the accessed addresses for the load and store instructions can not be statically determined. Without knowing those addresses, the source code can not be annotated appropriately for data cache simulation.
In this paper, we show an approach that is capable of resolving the accessed memory addresses based on the memory allocation mechanism. Applying this approach, the source code can be annotated to perform precise data cache simulation. The novelty of our methodology is that it is the first of its kind to take the memory allocation mechanism into account and thus can handle all the stack, data, heap and text sections.Moreover, a method is also proposed to handle pointer dereferences. In experiments, SLS with our approach yields almost identical cache miss rate and pattern when compared to the reference simulation. |
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| Title | Shared Cache Aware Task Mapping for WCRT Minimization |
| Author | *Huping Ding (National University of Singapore, Singapore), Yun Liang (Center for Energy-efficient Computing and Applications, School of EECS, Peking University, China), Tulika Mitra (National University of Singapore, Singapore) |
| Page | pp. 735 - 740 |
| Keyword | Worst-Case Execution Time (WCET), Worst-Case Response Time(WCRT), Task mapping, Shared cache modeling, Multi-core |
| Abstract | The Worst-Case Response Time (WCRT) of multi-tasking
applications running on multi-cores is an important metric for
real-time embedded systems. The WCRT is determined by the
mapping of the tasks to the cores (which determines load
balancing) and the Worst-Case Execution Time (WCET) of the
tasks. However, the WCET of a task is also influenced by the
conflicts in the shared cache from concurrently executing tasks
on other cores in a multi-core system. In other words, the
mapping of the tasks to the cores indirectly influences the
WCET of the tasks, which in turn impacts the WCRT of the entire
application. Thus the mapping of the tasks to the cores should
simultaneously maximize workload balance and minimize shared
cache interference. We propose an integer-linear programming
(ILP) formulation to achieve this objective. Experimental
evaluation shows that shared cache aware task mapping achieves
on an average 25% and 33% WCRT reduction for real-life and
synthetic applications, respectively, compared to traditional
approach that is agnostic to shared cache conflicts and solely
focuses on load balancing. |
| Slides |
| Title | Scratchpad Memory Aware Task Scheduling with Minimum Number of Preemptions on a Single Processor |
| Author | *Qing Wan, Hui Wu, Jingling Xue (University of New South Wales, Australia) |
| Page | pp. 741 - 748 |
| Keyword | Task Scheduling, Worst-Case Execution Time, Scratchpad Memory |
| Abstract | We propose a unified approach to the problem of scheduling a set of tasks with individual release times, deadlines and precedence constraints, and allocating the data of each task to the SPM (Scratchpad Memory) on a single processor system. Our approach consists of a task scheduling algorithm and an SPM allocation algorithm. The former constructs a feasible schedule incrementally, aiming to minimize the number of preemptions in the feasible schedule. The latter allocates a portion of the SPM to each task in an efficient way by employing a novel data structure, namely, the preemption graph. We have evaluated our approach and a previous approach by using six task sets. The results show that our approach achieves up to 20.31% on WCRT (Worst-Case Response Time) reduction over the previous approach. |
| Title | Scheduling Multiple Charge Migration Tasks in Hybrid Electrical Energy Storage Systems |
| Author | Qing Xie, Di Zhu, Yanzhi Wang (University of Southern California, U.S.A.), *Younghyun Kim, Naehyuck Chang (Seoul National University, Republic of Korea), Massoud Pedram (University of Southern California, U.S.A.) |
| Page | pp. 749 - 754 |
| Keyword | charge management, energy storage, charge migration, scheduling |
| Abstract | Hybrid electrical energy storage (HEES) systems are comprised of multiple banks of heterogeneous electrical energy storage (EES) elements with distinct properties. This paper defines and solves the problem of scheduling multiple charge migration tasks in HEES systems with the objective of minimizing the total energy drawn from the source banks. The solution approach consists of two steps: (i) Finding the best charging current profile and voltage level setting for the Charge Transfer Interconnect (CTI) bus for each charge migration task, and (ii) Merging and scheduling the charge migration tasks. Experimental results demonstrate improvements of up to 32.2% in the charge migration efficiency compared to baseline setups in an example HEES system. |
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