| Title | A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations |
| Author | *Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram (Univ. of Southern California, U.S.A.) |
| Page | pp. 75 - 80 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Controlled Placement of Standard Cell Memory Arrays for High Density and Low Power in 28nm FD-SOI |
| Author | *Adam Teman (EPFL, Switzerland), Davide Rossi (Univ. of Bologna, Italy), Pascal Meinerzhagen (EPFL, Switzerland), Luca Benini (Univ. of Bologna, Italy/ETH, Switzerland), Andreas Burg (EPFL, Switzerland) |
| Page | pp. 81 - 86 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design |
| Author | *Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan) |
| Page | pp. 87 - 93 |
| Detailed information (abstract, keywords, etc) | |
| Title | Stress-Aware P/G TSV Planning in 3D-ICs |
| Author | *Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany) |
| Page | pp. 94 - 99 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |