| Title | (Invited Paper) An Efficient Linear Time Triple Patterning Solver |
| Author | Haitong Tian (University of Illinois at Urbana-Champaign, U.S.A.), Hongbo Zhang (Synopsys Inc., U.S.A.), Zigang Xiao, *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.) |
| Page | pp. 208 - 213 |
| Keyword | Triple patterning, lithography, stitches |
| Abstract | Triple patterning lithography (TPL) has been recognized as one of the most promising techniques for 14/10nm technology node. In this paper, we applied triple patterning lithography on standard cell based designs, and proposed a novel algorithm to optimally solve the problem. The algorithm is able to find all legal stitch candidates, and guarantees to find a legal TPL decomposition with optimal number of stitches if one exists. Experimental results shows that the proposed algorithm is very efficient, which achieves 39.1% runtime improvement and 18.4% memory reduction compared with the state-of-the-art TPL algorithm on the same problem. |
| Title | (Invited Paper) Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs |
| Author | Tiago Reimann (Universidade Federal do Rio Grande do Sul, Brazil), Cliff C.N. Sze (IBM, U.S.A.), *Ricardo Reis (Universidade Federal do Rio Grande do Sul, Brazil) |
| Page | pp. 214 - 219 |
| Keyword | power optimization, physical synthesis, gate sizing |
| Abstract | Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent two discrete gate sizing contests organized by International Symposium on Physical Design. Since then, there are plenty of research papers published and new algorithms are proposed based on the ISPD 2013 contest formulation. However, almost all (new and old) papers in the literature ignore the details of how power-driven gate sizing fits in industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based gate sizing into our actual physical synthesis framework, and explain the challenges and issues we observed from the point of view of VLSI design flows. |
| Slides | |
| Title | (Invited Paper) Analytical Placement for Rectilinear Blocks |
| Author | *Yasuhiro Takashima (University of Kitakyushu, Japan) |
| Page | pp. 220 - 225 |
| Keyword | Rectilinear Block, Analytical Placement, Overlap Removable Length, Stable-LSE |
| Abstract | This paper proposes a fast analytical placement for rectilinear blocks. The LSI production method is also improved. As a result, there are much large number of elements on one chip. On the other hand, its turn-around-time is same as or less than those of the previous designs. To solve this difficulty, the reuse of the designed modules, that is, IPs, is promising. However, the LSI production improvement also leads larger numbers of IPs, while the shape of IP seems to be rectilinear. Thus, a fast analytical placement for rectilinear blocks is needed. In this paper, we enhance Overlap-Removable Length which has been introduced to the rectangle block placement to rectilinear block placement. We show the efficiency of the proposed method empirically. |
| Slides | |
| Title | (Invited Paper) IR to Routing Challenge and Solution for Interposer-Based Design |
| Author | *Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang (MediaTek, Taiwan) |
| Page | pp. 226 - 230 |
| Keyword | Routing, Interposer, IR drop |
| Abstract | A novel IR-aware chip and interposer co-design methodology is presented to handle both chip-interposer routing and micro-bump planning for IR drops. Based on bump rules and power information in a chip, the methodology analyzes the locations of micro bumps to meet IR constraints. For chip-interposer routing, the computational geometry techniques (e.g., Delaunay triangulation and Voronoi diagram) are applied to a network flow formulation for minimizing both IR drops and total wirelength. With the chip and interposer co-design flow, IR constraints can be met with 100% chip-interposer routing completion. Experimental results based on industry designs demonstrate the high-quality of our algorithm. |