| Title | Detailed-Routing-Driven Analytical Standard-Cell Placement |
| Author | *Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang (National Taiwan University, Taiwan) |
| Page | pp. 378 - 383 |
| Keyword | Placement, Routing, Routability, Global-/Detailed-Routing, Analytical Placement |
| Abstract | Due to the significant mismatch between global-routing congestions estimated during placement and the resulting design-rule violations in detailed routing, considering both global and detailed routability during placement is of particular importance for modern circuit designs. This paper presents an analytical standard-cell placement algorithm to optimize detailed routability with three major techniques: (1) A routability-driven wirelength model that directly minimizes routing congestion and wirelength simultaneously with no additional computational overhead in global placement. (2) A detailed-routability-aware whitespace allocation technique in legalization. (3) A multi-stage congestion-aware cell spreading method in detailed placement. Compared with the participating teams of the 2014 ISPD Detailed-Routing-Driven Placement Contest and a state-of-the-art routability-driven placer, our placer achieves the best quality in both detailed-routing violation and wirelength scores. |
| Title | An Approach to Anchoring and Placing High Performance Custom Digital Designs |
| Author | *Shih-Ying Liu (National Chiao Tung University/MediaTek Inc., Taiwan), Tung-Chieh Chen (Synopsys Inc., Taiwan), Hung-Ming Chen (National Chiao Tung University, Taiwan) |
| Page | pp. 384 - 389 |
| Keyword | Placement, Custom Digital |
| Abstract | Custom layouts of digital blocks are often used in mixed-signal designs in order to meet the critical performance requirements. Unlike traditional standard-cell based digital placement, custom-cell based digital placement may need additional manual help and intervention to achieve higher performance. The need for manual intervention is primarily due to the inability of modern analytical placers in delivering satisfactory performance on placing designs without pre-placed blocks. While most design flow works in a flat or top-down fashion, custom digital design generally works in a bottom-up fashion that there is no prior knowledge on I/O pin plan since it is changeable by the owners of modules. Without any or very few fixed I/O locations, modern analytical placers tend to produce unsatisfactory results. In this work, we propose a method, mimicking the process of making beds, to guide state-of-the-art analytical placers to deliver better placement results. With the crafted pseudo anchors and nets, total HPWL on Capo10.5 [1], mPL6 [2], NTUplace3 [3] and VDAPlace [4] have improved by 2.92%, 8.69%, 25.26% and 10.72% respectively on a set of industry custom digital designs and improved by 2.19%, 4.34%, 36.09%, and 14.27% respectively on Peko-Suite1 benchmarks. |
| Title | Non-Stitch Triple Patterning-Aware Routing Based on Conflict Graph Pre-Coloring |
| Author | *Po-Ya Hsu, Yao-Wen Chang (National Taiwan University, Taiwan) |
| Page | pp. 390 - 395 |
| Keyword | triple patterning lithography, routing, non-stitch triple patterning-aware routing, conflict graph |
| Abstract | Considering decomposition constraints earlier during routing becomes critical for realizing triple patterning lithography. In addition, stitches typically cause significant yield loss because of the overlay errors among different masks. As a result, leading foundries even get rid of the use of stitches in their design methodology. In order to completely avoid stitch-induced yield loss, we address the non-stitch triple patterning-aware routing problem. We observe that directly extending a state-of-the-art triple patterning-aware routing work to non-stitch routing might generate improper self-crossing nets and degrade routing quality due to sequential coloring for mask selection. To resolve these problems, we propose a new graph model to prevent self-crossing nets during routing and use a weighted conflict graph to globally consider net coloring. We then propose the first non-stitch triple patterning-aware routing scheme, which consists of two main stages: (1) conflict graph pre-coloring followed by (2) pre-coloring-based non-stitch routing. Experimental results show the effectiveness and efficiency of our routing scheme. |
| Slides | |
| Title | Cut Mask Optimization with Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing |
| Author | *Shao-Yun Fang (National Taiwan University of Science and Technology, Taiwan) |
| Page | pp. 396 - 401 |
| Keyword | self-aligned multiple patterning, cut mask optimization, SAMP-aware routing, wire planning |
| Abstract | Self-aligned quadruple patterning (SAQP) will be required for advanced sub-10nm nodes. However, cut masks used in SAQP are hardly manufacturable for arbitrary layouts because cut mask rules are limited by conventional 193nm lithography. To the best of our knowledge, existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks. |
| Slides | |
| Title | A Length Matching Routing Method for Disordered Pins in PCB Design |
| Author | *Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda University, Japan) |
| Page | pp. 402 - 407 |
| Keyword | PCB routing, length matching routing, EDA |
| Abstract | In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obtain a length matching routing. We initially check the longest common subsequence of pin pairs to assign layers for pins. Then, adopt single commodity flow to generate base routes. R-flip and C-flip are finally carried out to adjust the wire length. The experiments show that our algorithm generates the optimal routes with better wire balance within reasonable CPU times. |
| Slides | |