| Title | Approximation-Aware Scheduling on Heterogeneous Multi-Core Architectures |
| Author | *Cheng Tan, Thannirmalai Somu Muthukaruppan, Tulika Mitra (National University of Singapore, Singapore), Lei Ju (Shandong University, China) |
| Page | pp. 618 - 623 |
| Keyword | energy-efficiency, DVFS, TDP, QoS |
| Abstract | Embedded devices in the multi-core era are performance-per-watt optimized, rendering energy-efficiency important. The heterogeneity of multi-core platform makes the problem more complicated. Fortunately, the accommodation of minimal loss in accuracy for applications yields chances to improve energy-efficiency. In this paper, we introduce an approximation-aware scheduling framework for real-time tasks on the heterogeneous multi-core architectures. It efficiently schedules tasks running on the different cores with appropriate frequency under thermal design power constraint while minimizing energy consumption and maximizing the Quality-of-Service. |
| Slides |
| Title | Composing Real-Time Applications from Communicating Black-Box Components |
| Author | *Martin Becker (Real-Time Computer Systems, Technical University of Munich, Germany), Alejandro Masrur (Software Technology for Embedded Systems, Technical University Chemnitz, Germany), Samarjit Chakraborty (Real-Time Computer Systems, Technical University of Munich, Germany) |
| Page | pp. 624 - 629 |
| Keyword | Real-Time, Software, Components, Composition, Library |
| Abstract | To handle complexity, embedded software is usually divided into
components that are developed independently from each other and need then be integrated in a reliable and deterministic manner.
This involves buffering and synchronizing exchanged signals,
as well as finding a feasible execution schedule, which is a tedious
and error-prone procedure.
We propose a framework that automatically performs such an
integration, without requiring access to the components' source
code. The developer only needs to declare interface signals between
the components, connect them and define their execution periods. A
software library then synthesizes deterministic communication
mechanisms and provides a flexible, yet safe interface for
time-triggered execution.
Our approach does not require a run-time environment or a special
compiler, which makes it light-weight and amenable to be used on
embedded platforms with limited resources. |
| Slides |
| Title | Enhanced Partitioned Scheduling of Mixed-Criticality Systems on Multicore Platforms |
| Author | *Zaid Al-bayati (McGill University, Canada), Qingling Zhao (Zhejiang University, China), Ahmed Youssef (McGill University, Canada), Haibo Zeng (Virginia Tech, U.S.A.), Zonghua Gu (Zhejiang University, China) |
| Page | pp. 630 - 635 |
| Keyword | Mixed-criticality systems, scheduling, multicore |
| Abstract | Mixed Criticality Systems (MCS) have gained increasing
interest in the past few years due to their industrial relevance.
When mixed-criticality systems are implemented on multicore
architectures, several challenges arise such as the efficient
partitioning of these systems. In this paper, we address this issue by presenting a novel mixed-criticality partitioning algorithm, the Dual-Partitioned Mixed-Criticality (DPM) algorithm, that allows limited migration of LO-criticality tasks to enhance the efficiency of the partitioning while maintaining many of the advantages of partitioned systems. Experimental results show that DPM consistently outperforms existing mixed-criticality partitioning algorithms, for example, at utilizations of 0.8 or higher, DPM is able to schedule 17% more systems. |
| Title | Reducing Dynamic Dispatch Overhead (DDO) of SLDL-Synthesized Embedded Software |
| Author | Jiaxing Zhang, Sanyuan Tang, *Gunar Schirner (Northeastern University, U.S.A.) |
| Page | pp. 636 - 643 |
| Keyword | Embedded software, Software Synthesis, Optimization, SpecC, Compiler |
| Abstract | System-Level Design Languages (SLDL) allow component-oriented
specifications, e.g. for separating computation and communication.
This separation allows for a flexible model composition, refinement
and explorations. This flexibility, however, requires dynamic dispatch
during execution that degrades the simulation performance. After
synthesized to a target platform, the model re-composition is no
longer required. Then, the involved Dynamic Dispatch Overhead (DDO)
only limits performance without providing benefits. Thus, approaches
are needed for software synthesis to analyze model connectivity and
eliminate the DDO wherever possible.
This paper introduces a static dispatch type analysis as part of the
DDO-aware embedded C code synthesis from SLDL models. Our DDO-aware
software (SW) synthesis emits faster, more readable static dispatch
code whenever a static connectivity is determinable. By replacing
virtual functions with direct function calls, the DDO can be totally
eliminated allowing for aggressive inlining optimizations by the
compiler. We demonstrate the benefits of the improved SW synthesis on
a JPEG encoder, which runs up to 16% faster with DDO-reduction on an
ARM9-based HW/SW platform. Our approach combines the flexibility
benefits in specification modeling with efficient execution when
synthesized to embedded targets. |