| Title | Contact Pitch and Location Prediction for Directed Self-Assembly Template Verification |
| Author | Zigang Xiao, Yuelin Du, *Martin D.F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), He Yi, H.-S. Philip Wong (Stanford University, U.S.A.), Hongbo Zhang (Synopsys Inc., U.S.A.) |
| Page | pp. 644 - 651 |
| Keyword | Directed Self-Assembly, Machine Learning, Pitch Prediction, Verification, Design for Manufacturability |
| Abstract | In Directed Self-Assembly (DSA), the patterning variation in the templates is
very likely to affect the placement and shape of the final contact holes. However, rigorous DSA simulation is unacceptably slow for full chip verification. This paper presents a machine
learning based DSA verification method that is able to learn a model of high
accuracy in predicting the pitch size and hole location. The experimental
results show that our method achieves high accuracy and low time cost compared
to simulation-based methods. |
| Slides |
| Title | Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography |
| Author | *Yunfeng Yang, Wai-Shing Luk (Fudan University, China), Hai Zhou (Fudan University, China/Northwestern University, U.S.A.), Changhao Yan, Xuan Zeng (Fudan University, China), Dian Zhou (Fudan University, China/University of Texas at Dallas, U.S.A.) |
| Page | pp. 652 - 657 |
| Keyword | hybrid lithography, mulitple patterning, e-beam, layout decomposition, primal-dual |
| Abstract | As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and e-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion K-partition problem, where K is the number of masks in multiple patterning. Stitch minimization and EBL throughput are considered uniformly by adding a virtual vertex between two feature vertices for each stitch candidate during the conflict graph construction phase. For K = 2, we propose a primal-dual method for solving the underlying minimum odd-cycle cover problem efficiently. In addition, a chain decomposition algorithm is employed for removing all "non-cyclable" edges. For K > 2, we propose a random-initialized local search method that iteratively applies the primal-dual solver. Experimental results show that compared with a two-stage method, our proposed methods reduce the EBL usage by 64.4% with double patterning and 38.7% with triple patterning on average for the benchmarks. |
| Title | Polynomial Time Optimal Algorithm for Stencil Row Planning in E-Beam Lithography |
| Author | Daifeng Guo, Yuelin Du, *Martin D.F. Wong (University of Illinois at Urbana-Champaign, U.S.A.) |
| Page | pp. 658 - 664 |
| Keyword | E-Beam, Stencil Planning, 1D Character Row Ordering |
| Abstract | Electron beam lithography (EBL) is a very promising candidate for integrated circuit (IC) fabrication beyond the 10 nm technology node. To address its throughput issue, the Character Projection (CP) technique has been proposed, and its stencil planning can be optimized with aware of overlapping characters. However, the top level 2D stencil planning problem has been proved to be an NP-hard problem. As its most essential step, the 1D row ordering is believed hard as well, and no polynomial time optimal solution has been provided so far. In this paper, we propose a polynomial time optimal algorithm to solve the row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Proof and experimental results are also provided to verify the correctness and efficiency of our algorithm. |
| Title | Fast Mask Assignment Using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography |
| Author | *Yukihide Kohira (The University of Aizu, Japan), Tomomi Matsui (Tokyo Institute of Technology, Japan), Yoko Yokoyama, Chikaaki Kodama (Toshiba Corporation, Japan), Atsushi Takahashi (Tokyo Institute of Technology, Japan), Shigeki Nojima, Satoshi Tanaka (Toshiba Corporation, Japan) |
| Page | pp. 665 - 670 |
| Keyword | triple patterning lithography, LELECUT, mask assignment, positive semidefinite relaxation |
| Abstract | Recently, LELECUT type triple patterning lithography (TPL) technology, where the third mask is used to cut the patterns, is discussed to alleviate native conflict and overlay problems in LELELE type TPL. In this paper, we formulate LELECUT mask assignment problem which maximizes the compliance to the lithography and apply a positive semidefinite relaxation. In our proposed method, the positive semidefinite relaxation is defined by extracting cut candidates from the layout, and a mask assignment is obtained from an optimum solution of the relaxation by randomized rounding technique. |
| Title | Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning |
| Author | *Shao-Yun Fang (National Taiwan University of Science and Technology, Taiwan), Yi-Shu Tai, Yao-Wen Chang (National Taiwan University, Taiwan) |
| Page | pp. 671 - 676 |
| Keyword | self-aligned double patterning, layout decomposition, spacer-is-metal |
| Abstract | Self-aligned double patterning (SADP) has become a preferred double patterning technology, due to its better overlay controllability. Since there is only one satisfiability-based previous work on SIM-type layout decomposition, which typically has higher decomposition flexibility (especially for gridless designs), we propose an efficient graph-based SIM-type layout decomposition heuristic. The decomposition problem is first transformed into a constrained set-covering problem. Then, an efficient algorithm composed of a greedy heuristic followed by a partition-based solution refinement scheme is proposed. Experimental results show that the algorithm can efficiently derive a good decomposition solution with minimized pattern conflicts. |
| Slides |