| Title | AROMA: A Highly Accurate Microcomponent-Based Approach for Embedded Processor Power Analysis |
| Author | Zih-Ci Huang, *Chi-Kang Chen, Ren-Song Tsay (National Tsing Hua University, Taiwan) |
| Page | pp. 761 - 766 |
| Keyword | Embedded System, Power Optimization, Power Analysis, Power Profiling, Peak Power Analysis |
| Abstract | We propose a new embedded processor power analysis approach that maps instruction executions to microarchitecture components for highly efficient and accurate power evaluations, which are crucial for embedded system designs. We observe that in practice the execution of each high-level instruction in a processor always triggers same microcomponent activity sequence while the difference of power consumption values of different instructions is mainly due to timing variations caused by hazards and cache misses. Hence, by incorporating accurately pre-characterized microcomponent power consumption values into an efficient instruction-microcomponent processor timing simulation tool, we construct a highly accurate embedded processor power analysis tool. Additionally, based on the proposed approach we accurately and effortlessly capture the power waveform at any time point for power profiling, peak power and dynamic thermal distribution analysis. The experimental results show that the proposed approach is nearly as accurate as gate-level simulators, with an error rate of less than 1.2% while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. |
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| Title | Battery-Aware Mapping Optimization of Loop Nests for CGRAs |
| Author | *Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei (Institute of Microelectronics, Tsinghua University, China) |
| Page | pp. 767 - 772 |
| Keyword | reconfigurable computing, loop nests, energy consumption, polyhedral model |
| Abstract | Coarse-grained Reconfigurable Architecture (CGRA) is a promising mobile computing platform that provides both high performance and high energy efficiency. Since loop nests are usually mapped onto CGRA for acceleration, optimizing the mapping is an important goal for design of CGRAs. Moreover, how to reduce energy consumption also becomes one of primary concerns in using CGRAs. This paper makes three contributions: a) Proposing an energy consumption model for CGRA; b) Formulating loop nests mapping problem to minimize the battery charge loss; c) Extract an efficient heuristic algorithm called BPMap. Experiment results show that our methods improve the performance of the kernels and lower the energy consumption. |
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| Title | THOR: Orchestrated Thermal Management of Cores and Networks in 3D Many-Core Architectures |
| Author | *Jinho Lee, Junwhan Ahn, Kiyoung Choi (Seoul National University, Republic of Korea), Kyungsu Kang (Samsung Electronics, Republic of Korea) |
| Page | pp. 773 - 778 |
| Keyword | Dynamic thermal management, 3D stacking, network-on-chip, many-core |
| Abstract | Most previous researches on thermal management
of many-core architectures focus on the control of either core resources
or network resources only, even though both have significant
thermal impacts. This paper proposes a holistic thermal
management that applies dynamic voltage/frequency scaling
to cores and routers together to maximize system performance
under temperature constraint. The proposed method first determines
a power budget given in aggregate weighted power for
every pillar of vertically adjacent tiles. Then it performs voltage/
frequency assignment under the budget while exploiting the
characteristics of the applications. Experiments show that our
approach outperforms existing methods. |
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| Title | Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation |
| Author | Jianlei Yang (Tsinghua University/Intel Corporation, China), *Liwei Ma, Kang Zhao (Intel Corporation, China), Yici Cai (Tsinghua University, China), Tin-Fook Ngai (Intel Corporation, China) |
| Page | pp. 779 - 784 |
| Keyword | Real-Time, Power Estimation, RTL Instrumentation, Singular Value Decomposition (SVD) |
| Abstract | Early stage power estimation is critical for SoC architecture exploration and validation in modern VLSI design, but real-time, long time interval and accurate estimation is still challenging for system-level estimation and software/hardware tuning. This work proposes a model abstraction approach for real-time power estimation in the manner of machine learning. The singular value decomposition (SVD) technique is exploited to abstract the principle components of relationship between register toggling profile and accurate power waveform. The abstracted power model is automatically instrumented to RTL implementation and synthesized into FPGA platform for real-time power estimation by instrumenting the register toggling profile. The prototype implementation on three IP cores predicts the cycle-by-cycle power dissipation within 5% accuracy loss compared with a commercial power estimation tool. |
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