| Title | Clock Buffer Polarity Assignment Utilizing Useful Clock Skews for Power Noise Reduction |
| Author | *Deokjin Joo, Taewhan Kim (Seoul National Univ., Republic of Korea) |
| Page | pp. 226 - 231 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Buffer Insertion to Remove Hold Violations at Multiple Process Corners |
| Author | *Inhak Han, Daijoon Hyun, Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 232 - 237 |
| Detailed information (abstract, keywords, etc) | |
| Title | Speed Binning With High-Quality Structural Patterns From Functional Timing Analysis (FTA) |
| Author | *Louis Y.-Z. Lin, Charles H.-P. Wen (National Chiao Tung Univ., Taiwan) |
| Page | pp. 238 - 243 |
| Detailed information (abstract, keywords, etc) | |
| Title | Electromigration Recovery Modeling and Analysis under Time-Dependent Current and Temperature Stressing |
| Author | Xin Huang (Univ. of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics, U.S.A.), Taeyoung Kim (Univ. of California, Riverside, U.S.A.), Haibao Chen (Shanghai Jiao Tong Univ., China), *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.) |
| Page | pp. 244 - 249 |
| Detailed information (abstract, keywords, etc) | |