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The 12th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract    One Page (Not Separated) version
Author Index:   HERE

Session Schedule


Wednesday, January 24, 2007

ABCD
1K (Small Auditorium, 5F)
Opening Session and Keynote Address I
8:30 - 10:00
1A (Room 411+412)
DFM in Physical Design
10:15 - 12:20
1B (Room 413)
SoC Software Design and Performance Analysis
10:15 - 12:20
1C (Room 414+415)
Advances in High-Frequency and High-Speed Circuit Design and CAD
10:15 - 12:20
1D (Room 416+417)
University Design Contest
10:15 - 12:20
2A (Room 411+412)
New Techniques in Placement
13:30 - 15:35
2B (Room 413)
On Chip Communication Methodology
13:30 - 15:35
2C (Room 414+415)
Analog CAD Techniques: From Analysis to Verification
13:30 - 15:35
2D (Room 416+417)
SPECIAL SESSION: Design for Manufacturability
13:30 - 15:35
3A (Room 411+412)
Routing
16:00 - 18:05
3B (Room 413)
System Synthesis and Optimization Techniques
16:00 - 18:05
3C (Room 414+415)
Model Checking and Applications to Digital and Analog Circuits
16:00 - 18:05
3D (Room 416+417)
SPECIAL SESSION: Embedded Software for Multiprocessor Systems-on-Chip
16:00 - 18:05


Thursday, January 25, 2007

ABCD
2K (Small Auditorium, 5F)
Keynote Address II
9:00 - 10:00
4A (Room 411+412)
Model Order Reduction and Macromodeling
10:15 - 12:20
4B (Room 413)
System Level Modeling
10:15 - 12:20
4C (Room 414+415)
Logic Synthesis
10:15 - 12:20
4D (Room 416+417)
SPECIAL SESSION: EDA Challenges for Analog/RF
10:15 - 12:20
5A (Room 411+412)
Statistical Interconnect Modeling and Analysis
13:30 - 15:35
5B (Room 413)
Optimization Issues in Embedded Systems
13:30 - 15:35
5C (Room 414+415)
High-Level Synthesis
13:30 - 15:35
5D (Small Auditorium, 5F)
Designers' Forum Panel : Presilicon SoC HW/SW Verification
13:30 - 15:35
6A (Room 411+412)
Timing Modeling and Optimization
16:00 - 18:05
6B (Room 413)
Application Examples with Leading Edge Design Methodology
16:00 - 18:05
6C (Room 414+415)
Module/Circuit Synthesis
16:00 - 18:05
6D (Small Auditorium, 5F)
Designers' Forum: Low-power SoC Technologies
16:00 - 17:50


Friday, January 26, 2007

ABCD
3K (Small Auditorium, 5F)
Keynote Address III
9:00 - 10:00
7A (Room 411+412)
Advanced Methods for Leakage Reduction
10:15 - 12:20
7B (Room 413)
Uncertainty Aware Interconnect Design
10:15 - 12:20
7C (Room 414+415)
Test Cost Reduction Techniques
10:15 - 12:20
7D (Room 416+417)
SPECIAL SESSION: Multi-Processor Platforms for Next Generation Embedded Systems
10:15 - 12:20
8A (Room 411+412)
Advancement in Power Analysis and Optimization
13:30 - 15:35
8B (Room 413)
Electrical Optimization in Floorplanning/Placement
13:30 - 15:35
8C (Room 414+415)
Advances in Test and Diagnosis
13:30 - 15:35
8D (Small Auditorium, 5F)
Designers' Forum: High-speed Chip to Chip Signaling Solutions
13:30 - 15:35
9A (Room 411+412)
Power Efficient Design Techniques
16:00 - 18:05
9B (Room 413)
Leading Edge Design Methodology for Processors
16:00 - 18:05
9C (Room 414+415)
Satisfiability and Applications
16:00 - 18:05
9D (Small Auditorium, 5F)
Designers' Forum Panel: Top 10 Design Issues
16:00 - 18:05