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The 14th Asia and South Pacific Design Automation Conference

Session 2A  MPSoC and IP Integration
Time: 13:30 - 15:35 Tuesday, January 20, 2009
Location: Room 411+412
Chairs: Nozomu Togawa (Waseda Univ., Japan), Marcello Lajolo (NEC Laboratories America, United States)

2A-1 (Time: 13:30 - 13:55)
TitleTiming Variation-Aware Task Scheduling and Binding for MPSoC
Author*HaNeul Chon, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 137 - 142
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2A-2 (Time: 13:55 - 14:20)
TitleFlexible and Abstract Communication and Interconnect Modeling for MPSoC
Author*Katalin Popovici (TIMA Lab., France), Ahmed Jerraya (CEA-LETI, Minatec, France)
Pagepp. 143 - 148
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2A-3 (Time: 14:20 - 14:45)
TitlePartial Order Method for Timed Simulation of System-Level MPSoC Designs
Author*Eric Cheung, Harry Hsieh (Univ. of California, Riverside, United States), Felice Balarin (Cadence Design Systems, United States)
Pagepp. 149 - 154
Detailed information (abstract, keywords, etc)

2A-4 (Time: 14:45 - 15:10)
TitleA UML-Based Approach for Heterogeneous IP Integration
Author*Zhenxin Sun, Weng-Fai Wong (National Univ. of Singapore, Singapore)
Pagepp. 155 - 160
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