| Title | Improving Scalability of Model-Checking for Minimizing Buffer Requirements of Synchronous Dataflow Graphs |
| Author | Nan Guan (Northeastern University, China), *Zonghua Gu (Hong Kong University of Science and Technology, China), Wang Yi (Uppsala University, Sweden), Ge Yu (Northeastern University, China) |
| Page | pp. 715 - 720 |
| Keyword | SDF, model-checking |
| Abstract | Synchronous Dataflow (SDF) is a well-known model
of computation for dataflow-oriented applications such as embedded
systems for signal processing and multimedia. It is important
to minimize the buffer size requirements of applications generated
from SDF graphs, since memory space is often a scarce resource
in these systems due to cost or power consumption constraints.
Some authors have proposed to use model-checking
for finding the minimum buffer size requirements, but the scalability
of model-checking is limited by state space explosion. In
this paper, we present several techniques for reducing state space
size and improving scalability of model-checking by exploiting
problem-specific properties of SDF graphs. |
| Slides |
| Title | A Reverse-Encoding-based on-chip AHB Bus Tracer for Efficient Circular Buffer Utilization |
| Author | *Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang (National Sun Yat-Sen University, Taiwan) |
| Page | pp. 721 - 726 |
| Keyword | tracer, reverse encoding, pre-t trace, post-t trace, compression |
| Abstract | The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challenging problem since the initial state of the trace being compressed might be corrupted when wrapping around occurs and thus makes it difficult to reconstruct the trace from the incomplete information stored in the circular buffer. This paper proposes an efficient compression algorithm which is capable of compressing both pre-T and post-T traces. The algorithm is based on an innovative reverse encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a realtime on-chip AHB bus tracer and has been embedded in a 3D graphics SoC as an application example. The bus tracer costs only 44K gates and runs at 500MHz at 0.13um technology. Experiments have shown that this bus tracer achieves 100\% circular buffer utilization and captures 1.2x and 4.86x trace depths than state-of-the-art related work and conventional industrial approaches, respectively. |
| Slides |
| Title | Analyzing and Optimizing Energy Efficiency of Algorithms on DVS Systems: a First Step towards Algorithmic Energy Minimization |
| Author | *Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya University, Japan) |
| Page | pp. 727 - 732 |
| Keyword | Intratask dynamic voltage frequency scaling, Algorithmic energy minimization, Static voltage scaling, Sorting algorithms |
| Abstract | The energy efficiency at the algorithmic level on DVS systems and its analysis and optimization methods are presented. Given a problem the most energy efficient algorithm is {\em not} uniquely determined but dependent on multiple factors, including % the execution time distribution, intratask dynamic voltage scaling (IntraDVS) policies, the size of intermediate data structure, and the size of inputs. We show that at the algorithmic level principles behind energy optimization and performance optimization are {\em not} identical. We propose a metric for evaluating optimal energy efficiency of static voltage scaling (SVS) and a few new effective IntraDVS policies employing data flow information. Experimental results on sorting algorithms show the existence of several tradeoffs in terms of energy consumption. Transforming algorithms by employing problem specific knowledge and data flow information successfully improves their energy efficiency. |
| Slides |
| Title | Novel Task Migration Framework on Configurable Heterogeneous MPSoC Platforms |
| Author | Hao Shen, *Frédéric Pétrot (TIMA Laboratory, INP Grenoble, France) |
| Page | pp. 733 - 738 |
| Keyword | ASIP, migration framework, heterogeneous, MPSoC |
| Abstract | Heterogeneous MPSoC architectures can provide higher performance and flexibility with less power consumption and lower cost than homogeneous ones. However, as processor instruction sets of general heterogeneous MPSoCs are not identical, tasks migration between two heterogeneous processors is not possible. To enable this function, we propose to build one specific heterogeneous MPSoC platform in which all heterogeneous processors are based on the same core instruction set for the operating system realization. Different extended instructions can be added for different processors to improve the system performance. Tasks can be migrated from one processor to another only if the target processor has all instructions which can meet the execution requirement of this task. This paper concentrates on the infrastructure that is necessary to support the scheduling and migration of tasks between the processors. By using the Motion-JPEG case study, we confirm that our task migration framework can achieve
higher processor usage rate and more flexibility. |
| Slides |