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The 15th Asia and South Pacific Design Automation Conference

Session 10B  Emerging Circuits and Architectures
Time: 15:30 - 17:10 Thursday, January 21, 2010
Location: Room 101B
Chairs: Xiaoyang Zeng (Fudan Univ., China), Chun-Ming Huang (National Chip Implementation Center, Taiwan)

10B-1 (Time: 15:30 - 15:55)
TitleRule-Based Optimization of Reversible Circuits
Author*Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani (Amirkabir Univ. of Tech., Iran)
Pagepp. 849 - 854
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10B-2 (Time: 15:55 - 16:20)
TitleVariation Tolerant Logic Mapping for Crossbar Array Nano Architectures
AuthorCihan Tunc (Northeastern Univ., U.S.A.), *Mehdi Tahoori (Northeastern Univ./Karlsruhe Inst. of Tech., U.S.A.)
Pagepp. 855 - 860
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10B-3 (Time: 16:20 - 16:45)
TitleGeneralised Threshold Gate Synthesis based on AND/OR/NOT Representation of Boolean Function
Author*Marek Arkadiusz Bawiec, Maciej Nikodem (Wrocław Univ. of Tech., Poland)
Pagepp. 861 - 866
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10B-4 (Time: 16:45 - 17:10)
TitleNovel Dual-vth Independent-gate FinFET Circuits
AuthorMasoud Rostami, *Kartik Mohanram (Rice Univ., U.S.A.)
Pagepp. 867 - 872
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