| Title | Optimizing Power and Performance for Reliable On-Chip Networks |
| Author | Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, *Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan (Pennsylvania State Univ., U.S.A.) |
| Page | pp. 431 - 436 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Low Latency Wormhole Router for Asynchronous On-chip Networks |
| Author | *Wei Song, Doug Edwards (Univ. of Manchester, U.K.) |
| Page | pp. 437 - 443 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs |
| Author | Tsung-Yi Wu (National Changhua Univ. of Education, Taiwan), How-Rern Lin (Providence Univ., Taiwan), Tzi-Wei Kao, *Shi-Yi Huang, Tai-Lun Li (National Changhua Univ. of Education, Taiwan) |
| Page | pp. 444 - 449 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Workload Capacity Considering NBTI Degradation in Multi-core Systems |
| Author | Jin Sun, Roman Lysecky, Karthik Shankar (Univ. of Arizona, U.S.A.), Avinash Kodi (Ohio Univ., U.S.A.), Ahmed Louri, *Janet M. Wang (Univ. of Arizona, U.S.A.) |
| Page | pp. 450 - 455 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |