| Title | Co-design of Cyber-Physical Systems via Controllers with Flexible Delay Constraints |
| Author | *Dip Goswami, Reinhard Schneider, Samarjit Chakraborty (Technical University of Munich, Germany) |
| Page | pp. 225 - 230 |
| Keyword | Cyber-Physical Systems, Controller, Flexible Delay-contraints, FlexRay Protocol |
| Abstract | In this paper, we consider a cyber-physical architecture where control
applications are divided into multiple tasks, spatially distributed over various processing units that communicate via a shared bus. While
control signals are exchanged over the communication bus, they have
to wait for bus access and therefore experience a delay. We propose
certain (co-)design guidelines for (i) the communication schedule, and
(ii) the controller, such that stability of the control applications is guaranteed for more flexible communication delay constraints than what has been studied before. We illustrate the applicability of our design approach using the FlexRay dynamic segment as the communication medium for the processing units. |
| Slides |
| Title | Enhanced Heterogeneous Code Cache Management Scheme for Dynamic Binary Translation |
| Author | *Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang (National Tsing Hua University, Taiwan) |
| Page | pp. 231 - 236 |
| Keyword | code cache, binary translation |
| Abstract | Recently, Dynamic Binary Translation (DBT) technology has gained much attentions on embedded systems due to its various capabilities. However, the memory resource in embedded systems is often limited. This leads to the overhead of code re-translation and causes significant performance degradation. To reduce this overhead, Heterogeneous Code Cache (HCC), is proposed to split the code cache among SPM and main memory to avoid code re-translation. Although HCC is effective in handling applications with large working sets, it ignores the execution frequencies of program segments. Frequently executed program segments can be stored in main memory and suffer from large access latency. This causes significant performance loss. To address this problem, an enhanced Heterogeneous Code Cache management scheme which considers program behaviors is proposed in this paper. Experimental results show that the proposed management scheme can effectively improve the access ratio of SPM from 49.48% to 95.06%. This leads to 42.68% improvement of performance as compared with the management scheme proposed in the previous work. |
| Title | Fast Hybrid Simulation for Accurate Decoded Video Quality Assessment on MPSoC Platforms with Resource Constraints |
| Author | *Deepak Gangadharan (School of Computing, National University of Singapore, Singapore), Samarjit Chakraborty (Institute for Real-Time Computer Systems, Technical University of Munich, Germany), Roger Zimmermann (School of Computing, National University of Singapore, Singapore) |
| Page | pp. 237 - 242 |
| Keyword | MPSoC, MPEG-2 decoder, PSNR, resource constraints |
| Abstract | Multimedia decoders mapped onto MPSoC platforms
exhibit degraded video quality when the critical system resources
such as buffer and processor frequency are constrained.
Hence, it is essential for system designers to find the appropriate
mix of resources, living within the constraints, for a desired
output video quality. A naive approach to do this would be to run
expensive system simulations of the decoder tasks mapped onto
a model of the underlying MPSoC architecture. This turns out to
be inefficient when the input video library set has a large number
of video clips. We propose a fast hybrid simulation framework to
quantitatively estimate decoded video quality in the context of an
MPEG-2 decoder. Here, the workload of simulation heavy tasks
are estimated using accurate analytical models. The workload
of other light (but difficult to analytically model) tasks are
obtained from system simulations. This framework enables the
system designer to perform a fast trade-off analysis of the
system resources in order to choose the optimal combination
of resources for the desired video quality. When compared to a
naive system simulation approach, the hybrid simulation-based
framework shows speed-up factors of about 5x for motion and
8x for still videos. The results obtained using this framework
highlight important trade-offs such as the decoded video quality
(measured in terms of the peak signal to noise ratio (PSNR)) vs
buffer size and PSNR vs processor frequency. |
| Slides |
| Title | On the Interplay of Loop Caching, Code Compression, and Cache Configuration |
| Author | Marisha Rawlins, *Ann Gordon-Ross (University of Florida, U.S.A.) |
| Page | pp. 243 - 248 |
| Keyword | memory, cache, optimization |
| Abstract | Even though much previous work explores varying instruction cache optimization techniques individually, little work explores the combined effects of these techniques (i.e., do they complement or obviate each other). In this paper we explore the interaction of three optimizations: loop caching, cache tuning, and code compression. Results show that loop caching increases energy savings by as much as 26% compared to cache tuning alone and reduces decompression energy by as much as 73%. |
| Slides |