| Title | An Efficient Hybrid Engine to Perform Range Analysis and Allocate Integer Bit-widths for Arithmetic Circuits |
| Author | *Yu Pang (Chongqing Univ. of Posts and Telecommunications, China), Katarzyna Radecka, Zeljko Zilic (McGill Univ., Canada) |
| Page | pp. 455 - 460 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Register Pressure Aware Scheduling for High Level Synthesis |
| Author | *Rami Beidas, Wai Sum Mong, Jianwen Zhu (Univ. of Toronto, Canada) |
| Page | pp. 461 - 466 |
| Detailed information (abstract, keywords, etc) | |
| Title | Parallel Cross-Layer Optimization of High-Level Synthesis and Physical Design |
| Author | *James Williamson (Univ. of Colorado, Boulder, U.S.A.), Yinghai Lu (Northwestern Univ., U.S.A.), Li Shang (Univ. of Colorado, Boulder, U.S.A.), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China) |
| Page | pp. 467 - 472 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Network Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design |
| Author | Bei Yu, Sheqin Dong, *Yuchun Ma, Tao Lin, Yu Wang (Tsinghua Univ., China), Song Chen, Satoshi GOTO (Waseda Univ., Japan) |
| Page | pp. 473 - 478 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |