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The 16th Asia and South Pacific Design Automation Conference

Session 5C  High-Level and Logic Synthesis
Time: 13:40 - 15:40 Thursday, January 27, 2011
Location: Room 414+415
Chairs: Kiyoung Choi (Seoul National Univ., Republic of Korea), Shigeru Yamashita (Ritsumeikan Univ., Japan)

5C-1 (Time: 13:40 - 14:10)
TitleAn Efficient Hybrid Engine to Perform Range Analysis and Allocate Integer Bit-widths for Arithmetic Circuits
Author*Yu Pang (Chongqing Univ. of Posts and Telecommunications, China), Katarzyna Radecka, Zeljko Zilic (McGill Univ., Canada)
Pagepp. 455 - 460
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5C-2 (Time: 14:10 - 14:40)
TitleRegister Pressure Aware Scheduling for High Level Synthesis
Author*Rami Beidas, Wai Sum Mong, Jianwen Zhu (Univ. of Toronto, Canada)
Pagepp. 461 - 466
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5C-3 (Time: 14:40 - 15:10)
TitleParallel Cross-Layer Optimization of High-Level Synthesis and Physical Design
Author*James Williamson (Univ. of Colorado, Boulder, U.S.A.), Yinghai Lu (Northwestern Univ., U.S.A.), Li Shang (Univ. of Colorado, Boulder, U.S.A.), Hai Zhou (Northwestern Univ., U.S.A.), Xuan Zeng (Fudan Univ., China)
Pagepp. 467 - 472
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5C-4 (Time: 15:10 - 15:40)
TitleNetwork Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design
AuthorBei Yu, Sheqin Dong, *Yuchun Ma, Tao Lin, Yu Wang (Tsinghua Univ., China), Song Chen, Satoshi GOTO (Waseda Univ., Japan)
Pagepp. 473 - 478
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