| Title | (Panel Discussion) C-P-B Co-design/Co-verification Technology for DDR3 1.6G in Consumer Products |
| Author | Organizer: Koji Kato (Sony, Japan), Moderator: Makoto Nagata (Kobe University, Japan), Panelists: Keisuke Matsunami (Sony, Japan), Yoshinori Fukuba (Toshiba, Japan), Ji Zheng (Apache Design Solutions, U.S.A.), Jen-Tai Hsu (Global Unichip Corporation, U.S.A.), CT Chiu (ASE, Taiwan) |
| Abstract | Chip-package-board co-design/co-verification techniques for coming DDR3 1.6-Gbps interface for consumer applications. Such high-data rate needs to be realized with low-cost assembly like wire bonding on a FR-4 board with small number of layers. The panelists will be solicited from a set maker, a semiconductor manufacturer, an IP provider, a tool vendor, and assembly foundary. |
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