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The 16th Asia and South Pacific Design Automation Conference

Session 7B  NBTI and Power Gating
Time: 10:20 - 12:20 Friday, January 28, 2011
Location: Room 413
Chairs: Kimiyoshi Usami (Shibaura Institute of Technology, Japan), Toshio Sudo (Shibaura Institute of Technology, Japan)

7B-1 (Time: 10:20 - 10:50)
TitleControlling NBTI Degradation during Static Burn-in Testing
Author*Ashutosh Chakraborty, David Z. Pan (University of Texas at Austin, U.S.A.)
Pagepp. 597 - 602
KeywordNBTI, Burn-in, Performance, ILP, Static
AbstractNegative Bias Temperature Instability (NBTI) has emerged as the dominant PMOS device failure mechanism in the nanometer VLSI era. The extent of NBTI degradation of a PMOS device increases dramatically at elevated operating temperatures and supply voltages. Unfortunately, both these conditions are concurrently experienced by a VLSI chip during the process of burn-in testing. Therefore, burn-in testing can potentially causes significant NBTI degradation of the chip which can require designers to leave larger timing guard-bands during design phase. Our analysis shows that even during a short burn-in duration of 10 hours, the degradation accumulated can be as much 60% of the NBTI degradation experienced over 10 years of use at nominal conditions. Static burn-in testing in particular is observed to cause most NBTI degradation due to presence of a fixed vector which does not allow relaxation of NBTI effect as in the case of dynamic burn-in testing. The delay of benchmark circuits is observed to increase by over 10% due to static burn-in testing. We propose the first technique to reduce the NBTI degradation during static burn-in test by finding the minimum NBTI induced delay degradation vector (MDDV) based on timing criticality and threshold voltage change (Delta V_{TH}) sensitivity of the cells. Further, only a subset of the input pins need to be controlled for NBTI reduction, thus our technique allows other objectives (such as leakage reduction) to be considered simultaneously. Experimental results show NBTI induced V_TH and delay degradation can be reduced by as much as 25% and 20% respectively over several benchmark circuits using our proposed technique.

7B-2 (Time: 10:50 - 11:20)
TitleA Fine-Grained Technique of NBTI-Aware Voltage Scaling and Body Biasing for Standard Cell Based Designs
Author*Yongho Lee (Samsung Electronics, Republic of Korea), Taewhan Kim (Seoul National University, Republic of Korea)
Pagepp. 603 - 608
KeywordNBTI, Voltage scaling, Body biasing, Power
AbstractThis work addresses an important problem of minimizing the power consumption on standard cell based circuit while controlling the NBTI induced delay increase to meet the circuit timing constraint by simultaneously utilizing the effects of voltage scaling and (fine-grained) body biasing on both NBTI and power consumption. By a comprehensive analysis on the relations between the values of supply and body biasing voltages and the values of the resulting power consumption and NBTI induced delay, we precisely formulate the problem, and transform it into a problem of convex optimization to solve it efficiently.

7B-3 (Time: 11:20 - 11:50)
TitleNBTI-Aware Power Gating Design
AuthorMing-Chao Lee, *Yu-Guang Chen, Ding-Kai Huang, Shih-Chieh Chang (Dept. of CS, National Tsing Hua University, Taiwan)
Pagepp. 609 - 614
Keywordlow power, power gating, NBTI, reliability, leakage
AbstractA header-based power gating structure inserts PMOS as sleep transistors between the power rail and the circuit. Since PMOS sleep transistors in the functional mode are turned-on continuously, Negative Bias Temperature Instability (NBTI) influences the lifetime reliability of PMOS sleep transistors seriously. To tolerate NBTI effect, sizes of PMOS sleep transistors are normally over-sized. In this paper, we propose a novel NBTI-aware power gating architecture to extend the lifetime of PMOS sleep transistors. In our structure, sleep transistors are switched on/off periodically so that overall turned-on times of sleep transistors are reduced and sleep transistors are less influenced by NBTI effect. The experimental results show that our approach can achieve better lifetime extensions of PMOS sleep transistors than previous works and few area overheads.
Slides

7B-4 (Time: 11:50 - 12:20)
TitleRobust Power Gating Reactivation By Dynamic Wakeup Sequence Throttling
AuthorTung-Yeh Wu, Shih-Hsin Hu, *Jacob A. Abraham (The University of Texas at Austin, U.S.A.)
Pagepp. 615 - 620
Keywordpower gating, power supply noise, voltage drop, reactivation, wakeup
AbstractThe wakeup sequence for power gating techniques has become an important issue as the rush current typically causes a high voltage drop. This paper proposes a new wakeup scheme utilizing an on-chip detector which continuously monitors the power supply noise in real time. Therefore, this scheme is able to dynamically throttle the wakeup sequence according to ambient voltage level. As a result, even the adjacent active circuit blocks induce an unexpectedly high voltage drop, the possibility of the occurrence of excessive voltage drop is reduced significantly .