| Title | Robust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs |
| Author | *Jae-Seok Yang, Jiwoo Pak (University of Texas at Austin, U.S.A.), Xin Zhao, Sung Kyu Lim (Georgia Institute of Technology, U.S.A.), David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 621 - 626 |
| Keyword | TSV, CTS, stress, timing optimization, 3D IC |
| Abstract | 3D integration has new manufacturing and design challenges such as timing corner mismatch between tiers and device variation due to Through Silicon Via (TSV) induced stress. Timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers. TSV induced stress is another challenge in 3D Clock Tree Synthesis (CTS). Mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. In this paper, we propose clock tree design methodology with the following objectives: (a) to minimize clock period variation by assigning optimal z-location of clock buffers with an Integer Linear Program (ILP) formulation, (b) to prevent unwanted skew induced by the stress. In the results, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with our robust 3D CTS. |
| Title | Track Routing Optimizing Timing and Yield |
| Author | Xin Gao, *Luca Macchiarulo (Department of Electrical Engineering, University of Hawaii at Manoa, U.S.A.) |
| Page | pp. 627 - 632 |
| Keyword | Track routing, timing, yield, Geometric Programming |
| Abstract | In this paper, we propose a track routing algorithm for timing and yield optimization. The algorithm solves the problem in two stages: wire ordering, and wire spacing and sizing. The wire ordering problem is solved by an algorithm based on wire merging. For the wire spacing and sizing problem, we show that it can be represented as a Mixed Linear Geometric Programming (MLGP) problem which can be transformed into a convex optimization problem. Since general nonlinear convex optimization may take a long running time, we propose a heuristic that solves the problem much faster. Experimental results show that, compared to the algorithm that only optimizes yield, our algorithm is able to improve the minimum timing slack by 20%. |
| Title | Simultaneous Redundant Via Insertion and Line End Extension for Yield Optimization |
| Author | Shing-Tung Lin (National Tsing Hua University, Taiwan), Kuang-Yao Lee (Taiwan Semiconductor Manufacturing Company, Taiwan), *Ting-Chi Wang (National Tsing Hua University, Taiwan), Cheng-Kok Koh (Purdue University, U.S.A.), Kai-Yuan Chao (Intel Corporation, U.S.A.) |
| Page | pp. 633 - 638 |
| Keyword | integer linear program (ILP), redundant via insertion, line end extension, yield |
| Abstract | In this paper, we formulate a problem
of simultaneous redundant via insertion and line end
extension for via yield optimization. Our problem is
more general than previous works in the sense that
more than one type of line end extension is considered
and the objective function to be optimized directly
accounts for via yield. We present a zero-one integer
linear program based approach, that is equipped with
two speedup techniques, to solve the addressed problem
optimally. In addition, we describe how to modify
our approach to exactly solve a previous work. Extensive
experimental results are shown to demonstrate
the effectiveness and efficiency of our approaches. |
| Slides |
| Title | Pruning-based Trace Signal Selection Algorithm |
| Author | *Kang Zhao, Jinian Bian (Tsinghua University, China) |
| Page | pp. 639 - 644 |
| Keyword | Algorithm, silicon debug, state restoration, trace signal selection |
| Abstract | To improve the observability in the post-silicon validation, how to select the limited trace signals effectively for the data acquisition is the focus. This paper proposes an automated trace signal selection algorithm, which uses the pruning-based strategy to reduce the exploration space. The experiments indicate that the proposed algorithm can bring higher restoration ratios, and it is more effective compared to existing methods. |
| Slides |