| Title | High Performance Lithographic Hotspot Detection using Hierarchically Refined Machine Learning |
| Author | Duo Ding (University of Texas at Austin, U.S.A.), Andres Torres, Fedor Pikus (Mentor Graphics Corp., U.S.A.), *David Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 775 - 780 |
| Keyword | lithography hotspot detection, high performance, hierarchical machine learning, real manufacturing conditions, lithography friendly design |
| Abstract | Under real and continuously improving manufacturing
conditions, lithography hotspot detection faces several key
challenges. First, real hotspots become less but harder to fix at
post-layout stages; second, false alarm rate must be kept low
to avoid excessive and expensive post-processing hotspot
removal; third, full chip physical verification and optimization
require fast turn-around time. To address these issues, we
propose a high performance lithographic hotspot detection
flow with ultra-fast speed and high fidelity. It consists of
a novel set of hotspot signature definitions and a
hierarchically refined detection flow with powerful machine learning
kernels, ANN (artificial neural network) and SVM (support
vector machine). We have implemented our algorithm with
industry-strength engine under real manufacturing
conditions in 45nm process, and showed that it significantly
outperforms previous state-of-the-art algorithms in hotspot
detection false alarm rate (2.4X to 2300X reduction) and
simulation run-time (5X to 237X reduction), meanwhile
archiving similar or slightly better hotspot detection accuracies.
Such high performance lithographic hotspot detection
under real manufacturing conditions is especially suitable for
guiding lithography friendly physical design. |
| Title | Rapid Layout Pattern Classification |
| Author | *Jen-Yi Wuu (University of California, Santa Barbara, U.S.A.), Fedor G. Pikus, Andres Torres (Mentor Graphics Corporation, U.S.A.), Malgorzata Marek-Sadowska (University of California, Santa Barbara, U.S.A.) |
| Page | pp. 781 - 786 |
| Keyword | Hotspot detection, Machine learning, Design for manufacturabililty |
| Abstract | Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45nm and 32nm industrial designs. |
| Slides |
| Title | Mask Cost Reduction with Circuit Performance Consideration for Self-Aligned Double Patterning |
| Author | Hongbo Zhang, Yuelin Du, *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corporation, U.S.A.) |
| Page | pp. 787 - 792 |
| Keyword | Dense Line Cut, Cost reduction, Polygon simplification, Self-Aligned Double Patterning |
| Abstract | Double patterning lithography (DPL) is the enabling technology for printing in sub-32nm nodes. In the EDA literature, researchers have been focusing on double-exposure double-patterning (DEDP) DPL for printing arbitrary 2D features where the layout decomposition problem for double exposure is an interesting graph coloring problem. But due to overlay errors, it is very difficult for DEDP to print even 1D features. A more promising DPL technology is self-aligned double patterning (SADP) for 1D design. SADP first prints dense lines and then trims away the portions not on the design by a cut mask. The complexity of cut mask is very high, adding to the sky-rocketing manufacturing cost. In this paper we present a mask cost reduction method with circuit performance consideration for SADP. This is the first paper to focus on the mask cost reduction issue for SADP from a design perspective. We simplify the polygons on the cut mask, by formulating the problem as a constrained shortest path problem. Experimental results show that with a set of layouts in 28nm technology, we can largely reduce the complexity of cut polygons, with little impact on performance. |
| Title | Post-Routing Layer Assignment for Double Patterning |
| Author | *Jian Sun (State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China), Yinghai Lu, Hai Zhou (EECS Dept., Northwestern University, U.S.A.), Xuan Zeng (State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China) |
| Page | pp. 793 - 798 |
| Keyword | Double Patterning, Layer Assignment, NP-hard, Algorithm |
| Abstract | Double patterning lithography, where one-layer layout is decomposed into two masks, is believed to be inevitable for 32nm technology node of the ITRS roadmap. However, post-routing layer assignment, which decides the layout pattern on each layer, thus having great impact on double patterning related parameters, has not been explored in the merit of double patterning. In this paper, we propose a post-routing layer assignment algorithm for double patterning optimization. Our solution consists of three major phases: multi-layer assignment, single-layer double patterning, and via reduction. For phase one and three, multi-layer graph is constructed and dynamic programming is employed to solve optimization problem on this graph. In the second phase, single-layer double patterning is proved NP-hard and existing algorithm is implemented to optimize single layer double patterning problem. The proposed method is tested on CBL (Collaborative Benchmarking Laboratory) benchmarks and shows great performance. In comparison with single-layer double patterning, our method achieves 73% and 27% average reduction for unresolvable conflicts and stitches respectively, with only 9% increase of via number. When double patterning is constrained on only the bottom two metal layers as in current technology, these numbers become 62%, 8% and 0.42%. |
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