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The 17th Asia and South Pacific Design Automation Conference

Session 5A  Adaptive and Power-Efficient NoC Architectures
Time: 16:10 - 17:25 Wednesday, February 1, 2012
Location: Room 204B
Chairs: Karam Chatha (Arizona State Univ.), Yu Wang (Tsinghua Univ., China)

5A-1 (Time: 16:10 - 16:35)
TitleA Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs
Author*Hiroki Matsutani, Yuto Hirata (Keio Univ., Japan), Michihiro Koibuchi (NII, Japan), Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Hiroshi Nakamura (Univ. of Tokyo, Japan), Hideharu Amano (Keio Univ., Japan)
Pagepp. 407 - 412
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5A-2 (Time: 16:35 - 17:00)
TitleARB-NET: A Novel Adaptive Monitoring Platform for Stacked Mesh 3D NoC Architectures
Author*Amir-Mohammad Rahmani, Khalid Latif, Vaddina Kameswar Rao (Univ. of Turku/Turku Centre for Computer Science, Finland), Pasi Liljeberg, Juha Plosila, Hannu Tenhunen (Univ. of Turku, Finland)
Pagepp. 413 - 418
Detailed information (abstract, keywords, etc)

5A-3 (Time: 17:00 - 17:25)
TitleMemory-Aware Mapping and Scheduling of Tasks and Communications on Many-Core SoC
Author*Jinho Lee, Kiyoung Choi (Seoul National Univ., Republic of Korea)
Pagepp. 419 - 424
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